diff options
| author | Pradeep Goudagunta <pgoudagunta@nvidia.com> | 2010-12-17 16:15:05 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:49:02 -0700 |
| commit | 252214ee4c4d3fea96fb2ca53e3f601a70f6c3a1 (patch) | |
| tree | 19a8ed76054f22ed7f2db6664512abf49e83effe /drivers/serial | |
| parent | 3e954cc82f424fc6700be1d62259ec910265162d (diff) | |
[ARM] tegra:uart:Reseting Tx fifo in non fifo mode
If Tx fifo is reset in fifo mode then extra bytes were seen in receiver end
ASIC team recommended following as SW workaround
-Disable fifo mode
-Delay for 8x clock cycles
-Reset Tx fifo
-Enable fifo mode
Bug : 742346
Original-Change-Id: Ia091d0050dd7137e874acc2948e517b76c0743b6
Reviewed-on: http://git-master/r/13610
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: Iebc31029adbe2b4d5d56403d09cf5636a5160262
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/tegra_hsuart.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/serial/tegra_hsuart.c b/drivers/serial/tegra_hsuart.c index 4890def5e5c8..a74dbe6ad16d 100644 --- a/drivers/serial/tegra_hsuart.c +++ b/drivers/serial/tegra_hsuart.c @@ -362,8 +362,20 @@ static void wait_sym_time(struct tegra_uart_port *t, unsigned int syms) static void tegra_fifo_reset(struct tegra_uart_port *t, u8 fcr_bits) { unsigned char fcr = t->fcr_shadow; +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + /*Hw issue: Resetting tx fifo with non-fifo + mode to avoid any extra character to be sent*/ + fcr &= ~UART_FCR_ENABLE_FIFO; + uart_writeb(t, fcr, UART_FCR); + udelay(60); + fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + uart_writeb(t, fcr, UART_FCR); + fcr |= UART_FCR_ENABLE_FIFO; + uart_writeb(t, fcr, UART_FCR); +#else fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); uart_writeb(t, fcr, UART_FCR); +#endif uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */ wait_sym_time(t, 1); /* Wait for the flush to propagate. */ } |