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authorPradeep Goudagunta <pgoudagunta@nvidia.com>2011-02-02 12:10:55 +0530
committerVarun Colbert <vcolbert@nvidia.com>2011-02-03 19:07:37 -0800
commit2ad78027c3089bc68326d645d6c208182a526211 (patch)
tree5d62ce770b1506408528a70aa705c72acdf6b395 /drivers/serial
parent70c271da73807481a2a6405b63be30071b244c83 (diff)
arm: serial: tegra: add PORT_TEGRA port type
added new entry for PORT_TEGRA in serial8250 driver and updated flags and type of debug uart. Bug : 782543 Change-Id: I3e6c59f7a24731e92bd48197c6b1b22acdba8a8f Reviewed-on: http://git-master/r/17995 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Shail Dave <sdave@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/8250.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 24110f6f61e0..0243be5bded1 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -307,6 +307,14 @@ static const struct serial8250_config uart_config[] = {
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
+ [PORT_TEGRA] = {
+ .name = "Tegra",
+ .fifo_size = 32,
+ .tx_loadsz = 8,
+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_T_TRIG_01 |
+ UART_FCR_R_TRIG_01,
+ .flags = UART_CAP_FIFO,
+ },
};
#if defined(CONFIG_MIPS_ALCHEMY)
@@ -2158,6 +2166,9 @@ dont_test_tx_en:
* anyway, so we don't enable them here.
*/
up->ier = UART_IER_RLSI | UART_IER_RDI;
+ /* Use the receive timeout interrupt for tegra port*/
+ if (up->port.type == PORT_TEGRA)
+ up->ier |= UART_IER_RTOIE;
serial_outp(up, UART_IER, up->ier);
if (up->port.flags & UPF_FOURPORT) {