summaryrefslogtreecommitdiff
path: root/drivers/serial
diff options
context:
space:
mode:
authorColin Cross <ccross@google.com>2010-08-01 20:05:38 -0700
committerColin Cross <ccross@android.com>2010-10-06 16:28:08 -0700
commit40ac8c757b76127c7b204488de24e81cddaa3f5d (patch)
treea82a9b441b03b4694b5160fb7dd47dbefa01c615 /drivers/serial
parent3c8d2022b676e9cc76b981f9c1dcf3865812920a (diff)
serial: tegra_hsuart: Fix void return type on writel accessors
Signed-off-by: Colin Cross <ccross@google.com>
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/tegra_hsuart.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/serial/tegra_hsuart.c b/drivers/serial/tegra_hsuart.c
index 1ed206fb4c76..2433a8555270 100644
--- a/drivers/serial/tegra_hsuart.c
+++ b/drivers/serial/tegra_hsuart.c
@@ -117,20 +117,20 @@ static inline u8 uart_readb(struct tegra_uart_port *t, unsigned long reg)
return val;
}
-static inline u8 uart_writeb(struct tegra_uart_port *t, u8 val,
+static inline void uart_writeb(struct tegra_uart_port *t, u8 val,
unsigned long reg)
{
dev_vdbg(t->uport.dev, "%s: %p %03lx %02x\n",
__func__, t->uport.membase, reg << t->uport.regshift, val);
- return writeb(val, t->uport.membase + (reg << t->uport.regshift));
+ writeb(val, t->uport.membase + (reg << t->uport.regshift));
}
-static inline u8 uart_writel(struct tegra_uart_port *t, u32 val,
+static inline void uart_writel(struct tegra_uart_port *t, u32 val,
unsigned long reg)
{
dev_vdbg(t->uport.dev, "%s: %p %03lx %08x\n",
__func__, t->uport.membase, reg << t->uport.regshift, val);
- return writel(val, t->uport.membase + (reg << t->uport.regshift));
+ writel(val, t->uport.membase + (reg << t->uport.regshift));
}
static void tegra_set_baudrate(struct tegra_uart_port *t, unsigned int baud);