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authorFlorian Fainelli <f.fainelli@gmail.com>2019-10-25 11:34:58 -0700
committerFlorian Fainelli <f.fainelli@gmail.com>2020-09-06 12:43:02 -0700
commit10e7dd54cdaa00be8deb11a8cdb90faa804bdb19 (patch)
tree052f2a461f562b1d78f631084392dc74938f764e /drivers/soc/bcm
parent091353c88b3b4358aa5a0ec07bf53a2f2ac77206 (diff)
soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines
Change the RACPREFDATA(x) setting to prefetch the next 256-byte line after 4 consecutive lines have been used, instead of after 2 consecutive lines. This does improve the synthetic memcpy benchmark by an additional +0.5% on top of the previous change for Cortex-A72 CPUs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'drivers/soc/bcm')
-rw-r--r--drivers/soc/bcm/brcmstb/biuctrl.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c
index 28f69cc0df51..7f8dc302ae6e 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -174,7 +174,7 @@ static const u32 a72_b53_mach_compat[] = {
static void __init a72_b53_rac_enable_all(struct device_node *np)
{
unsigned int cpu;
- u32 enable = 0, pref_dist;
+ u32 enable = 0, pref_dist, shift;
if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
return;
@@ -184,9 +184,13 @@ static void __init a72_b53_rac_enable_all(struct device_node *np)
pref_dist = cbc_readl(RAC_CONFIG1_REG);
for_each_possible_cpu(cpu) {
+ shift = cpu * RAC_CPU_SHIFT + RACPREFDATA_SHIFT;
enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
- if (cpubiuctrl_regs == a72_cpubiuctrl_regs)
+ if (cpubiuctrl_regs == a72_cpubiuctrl_regs) {
+ enable &= ~(RACENPREF_MASK << shift);
+ enable |= 3 << shift;
pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
+ }
}
cbc_writel(enable, RAC_CONFIG0_REG);