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authorThierry Reding <treding@nvidia.com>2015-05-04 16:45:25 +0200
committerThierry Reding <treding@nvidia.com>2015-07-16 10:38:31 +0200
commit1dad36cdd5d20b4d7ceca5026553e86b3315b022 (patch)
treea8ce7779c763c7cf65db77d0a5c90628d09866d0 /drivers/soc
parent82df0e5e78d956ea3552f7315a4d559f657047da (diff)
soc/tegra: fuse: Add spare bit offset for Tegra210
The offset of the first spare bit register on Tegra210 is 0x380, but account for the fixed offset of 0x100 in the fuse accessor. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/tegra/fuse/fuse-tegra30.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
index 04e799e33ae3..882607bcaa6c 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra30.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
@@ -149,6 +149,7 @@ const struct tegra_fuse_soc tegra124_fuse_soc = {
static const struct tegra_fuse_info tegra210_fuse_info = {
.read = tegra30_fuse_read,
.size = 0x300,
+ .spare = 0x280,
};
const struct tegra_fuse_soc tegra210_fuse_soc = {