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| author | Daiane Angolini <daiane.angolini@foundries.io> | 2022-11-08 16:35:18 -0300 |
|---|---|---|
| committer | Daiane Angolini <daiane.angolini@foundries.io> | 2022-11-08 16:35:18 -0300 |
| commit | 28f04363b04142c45f8a29d0c32e21b060975e90 (patch) | |
| tree | 8578cfe035db9bd4b78a0c504512c5e7f89a96cb /drivers/spi/spi-s3c64xx.c | |
| parent | 7540d075c97713a4366a00b5c928261436b93d2d (diff) | |
| parent | bd8a595958a5b02e58cdd6fed82d4ebc77b1988a (diff) | |
Merge tag 'v5.15.75' into 5.15-2.1.x-imx
This is the 5.15.75 stable release
Conflicts:
arch/arm/boot/dts/imx6dl.dtsi
arch/arm/boot/dts/imx6q.dtsi
arch/arm/boot/dts/imx6sl.dtsi
arch/arm/boot/dts/imx6sll.dtsi
arch/arm/boot/dts/imx6sx.dtsi
arch/arm/boot/dts/imx7d-sdb.dts
drivers/char/hw_random/imx-rngc.c
drivers/dma/mxs-dma.c
drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
drivers/tty/serial/fsl_lpuart.c
drivers/usb/host/xhci.h
Signed-off-by: Daiane Angolini <daiane.angolini@foundries.io>
Diffstat (limited to 'drivers/spi/spi-s3c64xx.c')
| -rw-r--r-- | drivers/spi/spi-s3c64xx.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 8755cd85e83c..90c70d53e85e 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -85,6 +85,7 @@ #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) +#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) @@ -661,6 +662,13 @@ static int s3c64xx_spi_prepare_message(struct spi_master *master, return 0; } +static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi) +{ + struct spi_controller *ctlr = spi->controller; + + return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX; +} + static int s3c64xx_spi_transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *xfer) @@ -1130,6 +1138,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; master->prepare_message = s3c64xx_spi_prepare_message; master->transfer_one = s3c64xx_spi_transfer_one; + master->max_transfer_size = s3c64xx_spi_max_transfer_size; master->num_chipselect = sci->num_cs; master->dma_alignment = 8; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |