diff options
| author | Ashwini Ghuge <aghuge@nvidia.com> | 2012-06-20 13:52:45 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-07-12 10:12:10 +0530 |
| commit | 5f8764018b3b338e089036897ecc6205de054316 (patch) | |
| tree | 07bc55b7d3090a3c4a6c4e8fe44e779031f3e065 /drivers/spi/spi-tegra.c | |
| parent | e67e24c96227a5c3136dc03249cfe2a9dc6759e5 (diff) | |
spi: tegra: dump registers when error occurs
When any error occurs in spi communication,
dump the spi registers for debug purpose
Change-Id: I5cf226d4b504c95a6abb8dcf5b8c0ba1ef44271c
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/109466
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'drivers/spi/spi-tegra.c')
| -rw-r--r-- | drivers/spi/spi-tegra.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c index b6c1eaf1160b..6c67e3fb0fa6 100644 --- a/drivers/spi/spi-tegra.c +++ b/drivers/spi/spi-tegra.c @@ -591,6 +591,7 @@ static int spi_tegra_start_dma_based_transfer( udelay(1); wmb(); } + tspi->dma_control_reg = val; val |= SLINK_DMA_EN; spi_tegra_writel(tspi, val, SLINK_DMA_CTL); @@ -628,6 +629,7 @@ static int spi_tegra_start_cpu_based_transfer( udelay(1); wmb(); } + tspi->dma_control_reg = val; val |= SLINK_DMA_EN; spi_tegra_writel(tspi, val, SLINK_DMA_CTL); return 0; @@ -1046,6 +1048,9 @@ static void handle_cpu_based_xfer(void *context_data) (tspi->status_reg & SLINK_BSY)) { dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n", __func__, tspi->status_reg); + dev_err(&tspi->pdev->dev, "%s 0x%08x:0x%08x:0x%08x\n", + __func__, tspi->command_reg, tspi->command2_reg, + tspi->dma_control_reg); tegra_periph_reset_assert(tspi->clk); udelay(2); tegra_periph_reset_deassert(tspi->clk); @@ -1134,6 +1139,9 @@ static irqreturn_t spi_tegra_isr_thread(int irq, void *context_data) if (err) { dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n", __func__, tspi->status_reg); + dev_err(&tspi->pdev->dev, "%s 0x%08x:0x%08x:0x%08x\n", + __func__, tspi->command_reg, tspi->command2_reg, + tspi->dma_control_reg); tegra_periph_reset_assert(tspi->clk); udelay(2); tegra_periph_reset_deassert(tspi->clk); |