diff options
| author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | 2015-10-28 15:13:42 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-10-30 11:18:05 +0900 |
| commit | b7c08cf85c9a3a4b05474b7acacc9fbce8fb3eaf (patch) | |
| tree | 9dbec39b606014d645f16cc0195de40ff43b2f58 /drivers/spi | |
| parent | 8b136baa5892f25bba0373d6eb0f5f84efc93986 (diff) | |
spi: pxa2xx: Add support for Intel Broxton
LPSS SPI in Intel Broxton is otherwise the same than in Intel Sunrisepoint
but it supports up to four chip selects per port and has different FIFO
thresholds. Patch adds support for two Broxton SoC variants.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-pxa2xx.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index a5c2dce7d0a3..f759c082f0f7 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -116,6 +116,16 @@ static const struct lpss_config lpss_platforms[] = { .tx_threshold_lo = 32, .tx_threshold_hi = 56, }, + { /* LPSS_BXT_SSP */ + .offset = 0x200, + .reg_general = -1, + .reg_ssp = 0x20, + .reg_cs_ctrl = 0x24, + .reg_capabilities = 0xfc, + .rx_threshold = 1, + .tx_threshold_lo = 16, + .tx_threshold_hi = 48, + }, }; static inline const struct lpss_config @@ -130,6 +140,7 @@ static bool is_lpss_ssp(const struct driver_data *drv_data) case LPSS_LPT_SSP: case LPSS_BYT_SSP: case LPSS_SPT_SSP: + case LPSS_BXT_SSP: return true; default: return false; @@ -1152,6 +1163,7 @@ static int setup(struct spi_device *spi) case LPSS_LPT_SSP: case LPSS_BYT_SSP: case LPSS_SPT_SSP: + case LPSS_BXT_SSP: config = lpss_get_config(drv_data); tx_thres = config->tx_threshold_lo; tx_hi_thres = config->tx_threshold_hi; @@ -1313,6 +1325,14 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { /* SPT-H */ { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, + /* BXT */ + { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, + { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, + { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, + /* APL */ + { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, + { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, + { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, { }, }; |