diff options
| author | Shardar Shariff Md <smohammed@nvidia.com> | 2013-10-21 16:16:10 +0530 |
|---|---|---|
| committer | Laxman Dewangan <ldewangan@nvidia.com> | 2013-10-21 05:57:19 -0700 |
| commit | b0d979c91f815324afa2e978f805018310657b12 (patch) | |
| tree | 6172e4479d0ef3a3170d4ac4eb2118498bbf7746 /drivers/spi | |
| parent | b000ed105979f7bccf4e6eed741fc454251e685c (diff) | |
arm: t124: spi: Fix in setting RX_TAP_DELAY
RX_TAP_DELAY should be set even if controller data(cdata)
as tap delay should be set depending on speed
Change-Id: Ia584be5c6bfd1e71166b4241ff127c22e1a7aeaf
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/301756
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-tegra114.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 37d6c85dcd35..3a88a8b29c46 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -781,20 +781,33 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi, u32 command2_reg; u32 rx_tap_delay; u32 tx_tap_delay; + int rx_clk_tap_delay; + + rx_clk_tap_delay = cdata->rx_clk_tap_delay; #ifdef CONFIG_ARCH_TEGRA_12x_SOC - if (cdata->rx_clk_tap_delay == 0) { + if (rx_clk_tap_delay == 0) if (speed > SPI_SPEED_TAP_DELAY_MARGIN) - cdata->rx_clk_tap_delay = + rx_clk_tap_delay = SPI_DEFAULT_RX_TAP_DELAY; - } #endif - rx_tap_delay = min(cdata->rx_clk_tap_delay, 63); + rx_tap_delay = min(rx_clk_tap_delay, 63); tx_tap_delay = min(cdata->tx_clk_tap_delay, 63); command2_reg = SPI_TX_TAP_DELAY(tx_tap_delay) | SPI_RX_TAP_DELAY(rx_tap_delay); tegra_spi_writel(tspi, command2_reg, SPI_COMMAND2); } else { - tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2); + u32 command2_reg; + command2_reg = tspi->def_command2_reg; +#ifdef CONFIG_ARCH_TEGRA_12x_SOC + if (speed > SPI_SPEED_TAP_DELAY_MARGIN) { + command2_reg = command2_reg & + (~SPI_RX_TAP_DELAY(63)); + command2_reg = command2_reg | + SPI_RX_TAP_DELAY( + SPI_DEFAULT_RX_TAP_DELAY); + } +#endif + tegra_spi_writel(tspi, command2_reg, SPI_COMMAND2); } } else { command1 = tspi->command1_reg; |