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authorKunal Agrawal <kunala@nvidia.com>2012-10-23 14:12:38 +0530
committerDan Willemsen <dwillemsen@nvidia.com>2013-09-14 01:13:07 -0700
commit6ffda4a2a5b74df145f5f6b41583c937eb39e218 (patch)
tree1836e6fbff3214e773d701ce5003ec4d7a2789ae /drivers/spi
parentc33ea529199187e596517150fef3c4f71b045936 (diff)
spi: tegra11: set value of SPI FIFO depth
The value of SPI FIFO depth has been now set to 64. Change-Id: I9c1ab1bddc4635d4ec1696f5763a5822d688ad71 Signed-off-by: Kunal Agrawal <kunala@nvidia.com> Reviewed-on: http://git-master/r/146822 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: Rd3e4390529d444caf36124a7e5b0b08e0da2656b
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-tegra11.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-tegra11.c b/drivers/spi/spi-tegra11.c
index bfa04fc968d6..80fc92d670b8 100644
--- a/drivers/spi/spi-tegra11.c
+++ b/drivers/spi/spi-tegra11.c
@@ -151,7 +151,7 @@
#define SPI_TX_FIFO 0x108
#define SPI_RX_FIFO 0x188
#define MAX_CHIP_SELECT 4
-#define SPI_FIFO_DEPTH 32
+#define SPI_FIFO_DEPTH 64
#define DATA_DIR_TX (1 << 0)
#define DATA_DIR_RX (1 << 1)