diff options
| author | Grant Likely <grant.likely@secretlab.ca> | 2008-10-08 09:02:11 -0600 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2008-10-08 09:02:11 -0600 |
| commit | a897ea13f7a801e6baba8d4985f459042712244c (patch) | |
| tree | 580ce1aee753c3e1e7963e252beaf10ac8d87df6 /drivers/spi | |
| parent | 7c12d906f4ef690c65e60111375856640f63a545 (diff) | |
powerpc/mpc5200: fix build warnings on mpc52xx_psc_spi driver
The register definitions have been changed for the mpc5200 PSC ports
to cover some of the changes in the mpc5200b. One change is that the
ccr register is now a u32 instead of a u16. However, for the purposes
of this driver we want to continue to use 16 bit access to avoid
changing the existing (working) behaviour.
This patch allows the driver to continue to do 16 bit accesses without
the compiler complaining about it.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/mpc52xx_psc_spi.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c index 25eda71f4bf4..cdb3d3191719 100644 --- a/drivers/spi/mpc52xx_psc_spi.c +++ b/drivers/spi/mpc52xx_psc_spi.c @@ -108,13 +108,13 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi) * Because psc->ccr is defined as 16bit register instead of 32bit * just set the lower byte of BitClkDiv */ - ccr = in_be16(&psc->ccr); + ccr = in_be16((u16 __iomem *)&psc->ccr); ccr &= 0xFF00; if (cs->speed_hz) ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; else /* by default SPI Clk 1MHz */ ccr |= (MCLK / 1000000 - 1) & 0xFF; - out_be16(&psc->ccr, ccr); + out_be16((u16 __iomem *)&psc->ccr, ccr); mps->bits_per_word = cs->bits_per_word; if (mps->activate_cs) @@ -347,7 +347,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps) /* Configure 8bit codec mode as a SPI master and use EOF flags */ /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */ out_be32(&psc->sicr, 0x0180C800); - out_be16(&psc->ccr, 0x070F); /* by default SPI Clk 1MHz */ + out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */ /* Set 2ms DTL delay */ out_8(&psc->ctur, 0x00); |