diff options
| author | Helen Fornazier <helen.fornazier@gmail.com> | 2015-03-26 14:09:16 -0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-03-27 00:10:40 +0100 |
| commit | 82736d2244a059962bf9efec3338036ae9464986 (patch) | |
| tree | 0a400cbb38c944a7e7600c86b0479bc7e620906d /drivers/staging/sm750fb/ddk750_chip.c | |
| parent | ce02a16ae444f8a80877d660e41f162f7b2a967a (diff) | |
staging: sm750fb: Add space before if statement
This patch fix the checkpatch.pl warning:
ERROR: space required before the open parenthesis '('
Signed-off-by: Helen Fornazier <helen.fornazier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/sm750fb/ddk750_chip.c')
| -rw-r--r-- | drivers/staging/sm750fb/ddk750_chip.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c index 3d228f4fc7c9..49e26bd0f6ce 100644 --- a/drivers/staging/sm750fb/ddk750_chip.c +++ b/drivers/staging/sm750fb/ddk750_chip.c @@ -87,7 +87,7 @@ unsigned int getChipClock(void) { pll_value_t pll; #if 1 - if(getChipType() == SM750LE) + if (getChipType() == SM750LE) return MHz(130); #endif @@ -225,7 +225,7 @@ unsigned int ddk750_getVMSize(void) unsigned int data; /* sm750le only use 64 mb memory*/ - if(getChipType() == SM750LE) + if (getChipType() == SM750LE) return MB(64); /* for 750,always use power mode0*/ @@ -252,7 +252,7 @@ int ddk750_initHw(initchip_param_t * pInitParam) unsigned int ulReg; #if 0 //move the code to map regiter function. - if(getChipType() == SM718) { + if (getChipType() == SM718) { /* turn on big endian bit*/ ulReg = PEEK32(0x74); /* now consider register definition in a big endian pattern*/ @@ -272,7 +272,7 @@ int ddk750_initHw(initchip_param_t * pInitParam) ulReg = FIELD_SET(ulReg,CURRENT_GATE,LOCALMEM,ON); setCurrentGate(ulReg); - if(getChipType() != SM750LE) { + if (getChipType() != SM750LE) { /* set panel pll and graphic mode via mmio_88 */ ulReg = PEEK32(VGA_CONFIGURATION); ulReg = FIELD_SET(ulReg,VGA_CONFIGURATION,PLL,PANEL); @@ -444,7 +444,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll) /* for MXCLK register , no POD provided, so need be treated differently */ - if(pll->clockType != MXCLK_PLL) { + if (pll->clockType != MXCLK_PLL) { xparm = &xparm_PIXEL[0]; xcnt = sizeof(xparm_PIXEL)/sizeof(xparm_PIXEL[0]); } else { @@ -466,11 +466,11 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll) M += fl_quo * X / 10000; /* round step */ M += (fl_quo*X % 10000)>5000?1:0; - if(M < 256 && M > 0) { + if (M < 256 && M > 0) { unsigned int diff; tmpClock = pll->inputFreq *M / N / X; diff = absDiff(tmpClock,request_orig); - if(diff < miniDiff) { + if (diff < miniDiff) { pll->M = M; pll->N = N; pll->OD = xparm[d].od; |