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authorStefan Agner <stefan@agner.ch>2014-07-02 18:02:56 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-07-10 16:03:59 -0700
commit90abef91c5974d3d4845d64fd75a319fb20f6e6b (patch)
tree7855103964528f6e0b7e600381d2c7458998e953 /drivers/tty/serial
parentae84db9661cafc63d179e1d985a2c5b841ff0ac4 (diff)
serial: fsl_lpuart: move DMA RX timeout calculation
The DMA RX timeout calculation is done based on FIFO buffer size and port timeout when setting up DMA. However, both variables are not necessarily initialized at DMA initialization time, which can lead to a division by zero. Move the timeout calculation to set_termios where both variables are initialized. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial')
-rw-r--r--drivers/tty/serial/fsl_lpuart.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index c5ad567cab8d..5fde6da6ba20 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -720,13 +720,6 @@ static int lpuart_dma_rx_request(struct uart_port *port)
sport->dma_rx_buf_bus = dma_bus;
sport->dma_rx_in_progress = 0;
- sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
- FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
- sport->rxfifo_size / 2;
-
- if (sport->dma_rx_timeout < msecs_to_jiffies(20))
- sport->dma_rx_timeout = msecs_to_jiffies(20);
-
return 0;
}
@@ -918,6 +911,17 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
/* update the per-port timeout */
uart_update_timeout(port, termios->c_cflag, baud);
+ if (sport->lpuart_dma_use) {
+ /* Calculate delay for 1.5 DMA buffers */
+ sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
+ FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
+ sport->rxfifo_size / 2;
+ dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
+ sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
+ if (sport->dma_rx_timeout < msecs_to_jiffies(20))
+ sport->dma_rx_timeout = msecs_to_jiffies(20);
+ }
+
/* wait transmit engin complete */
while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
barrier();