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authorBarry Song <Baohua.Song@csr.com>2014-05-05 08:05:51 +0800
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-05-28 12:22:43 -0700
commit205c384f73e56d6b7d309b883a2064cd07ab5427 (patch)
tree4752b3b84ee37e82a438b2be8591d7ff4ba3f0eb /drivers/tty
parent717e1cb22f01ddeaaeddc126fed43f975c920d97 (diff)
serial: sirf: move to writel for TXFIFO instead of writeb
All SiRFSoC UART registers are in 32-bits. If we use writeb for TXFIFO, actually all of 32-bits are still written, for TXTIFO, only low 8-bits are valid, so in prima2&atlas6, this causes no problem. But in the new atlas7, using writeb to write UART registers will cause an imprecise data abort as HW does check the "wrong" writeb. So move to writel and this also makes the code consistent with sirfsoc_uart_pio_tx_chars() in which we use writel. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/sirfsoc_uart.c2
-rw-r--r--drivers/tty/serial/sirfsoc_uart.h2
2 files changed, 1 insertions, 3 deletions
diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c
index 68b0fd4b9a6a..845548cf05f8 100644
--- a/drivers/tty/serial/sirfsoc_uart.c
+++ b/drivers/tty/serial/sirfsoc_uart.c
@@ -1228,7 +1228,7 @@ static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
while (rd_regl(port,
ureg->sirfsoc_tx_fifo_status) & ufifo_st->ff_full(port->line))
cpu_relax();
- wr_regb(port, ureg->sirfsoc_tx_fifo_data, ch);
+ wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch);
}
static void sirfsoc_uart_console_write(struct console *co, const char *s,
diff --git a/drivers/tty/serial/sirfsoc_uart.h b/drivers/tty/serial/sirfsoc_uart.h
index 8a6eddad2f3c..4280819e1888 100644
--- a/drivers/tty/serial/sirfsoc_uart.h
+++ b/drivers/tty/serial/sirfsoc_uart.h
@@ -441,9 +441,7 @@ struct sirfsoc_uart_port {
/* Register Access Control */
#define portaddr(port, reg) ((port)->membase + (reg))
-#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
-#define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
/* UART Port Mask */