diff options
| author | Thinh Nguyen <Thinh.Nguyen@synopsys.com> | 2019-08-08 16:39:42 -0700 |
|---|---|---|
| committer | Felipe Balbi <felipe.balbi@linux.intel.com> | 2019-08-09 08:31:38 +0300 |
| commit | 4749e0e61241cc121de572520a39dab365b9ea1d (patch) | |
| tree | 9bb5f9f08c454d35eed983c0e2bd2ef70e5f3612 /drivers/usb/dwc3/core.h | |
| parent | b2a3974253d32374af556541141d7fdad8fe2ce0 (diff) | |
usb: dwc3: Update soft-reset wait polling rate
Starting from DWC_usb31 version 1.90a and later, the DCTL.CSFRST bit
will not be cleared until after all the internal clocks are synchronized
during soft-reset. This may take a little more than 50ms. Set the
polling rate at 20ms instead.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb/dwc3/core.h')
| -rw-r--r-- | drivers/usb/dwc3/core.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 3dd783b889cb..1c8b349379af 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1137,6 +1137,8 @@ struct dwc3 { #define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31) #define DWC3_USB31_REVISION_160A (0x3136302a | DWC3_REVISION_IS_DWC31) #define DWC3_USB31_REVISION_170A (0x3137302a | DWC3_REVISION_IS_DWC31) +#define DWC3_USB31_REVISION_180A (0x3138302a | DWC3_REVISION_IS_DWC31) +#define DWC3_USB31_REVISION_190A (0x3139302a | DWC3_REVISION_IS_DWC31) u32 version_type; |