diff options
| author | Narendra Damahe <ndamahe@nvidia.com> | 2011-04-29 12:01:04 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-05-05 14:31:23 -0700 |
| commit | e89db217d6ca866a55dcb0c0023624c57ec81cf3 (patch) | |
| tree | c3640ffa246f18403f91738ce0d755d79a102b46 /drivers/usb/gadget | |
| parent | 4dad57c5a8b3c1695ff437c443692bfa12111e8f (diff) | |
arm:tegra: USB EMC busy hint correction
EMC busy hint correction
Refer Bug 820214 for details
Change-Id: I18130d8fb17d5ed5b4629de2e22aea299915a9e6
Reviewed-on: http://git-master/r/29866
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'drivers/usb/gadget')
| -rw-r--r-- | drivers/usb/gadget/fsl_tegra_udc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/usb/gadget/fsl_tegra_udc.c b/drivers/usb/gadget/fsl_tegra_udc.c index 822a63d19315..a20802a80c75 100644 --- a/drivers/usb/gadget/fsl_tegra_udc.c +++ b/drivers/usb/gadget/fsl_tegra_udc.c @@ -53,7 +53,13 @@ int fsl_udc_clk_init(struct platform_device *pdev) } clk_enable(emc_clk); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + /* Set DDR busy hints to 150MHz. For Tegra 2x SOC, DDR rate is half of EMC rate */ clk_set_rate(emc_clk, 300000000); +#else + /* Set DDR busy hints to 150MHz. For Tegra 3x SOC DDR rate equals to EMC rate */ + clk_set_rate(emc_clk, 150000000); +#endif /* we have to remap the registers ourselves as fsl_udc does not * export them for us. |