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authorFelipe Balbi <balbi@ti.com>2014-02-25 14:08:51 -0600
committerFelipe Balbi <balbi@ti.com>2014-03-05 09:44:49 -0600
commit183ca11179f6d3b99e0431bae6acb84350b82dea (patch)
treea3903014d73ad0ff925809dd34c42acc9de4f8ca /drivers/usb
parentf3af36511e60669a2b5644d17378c7ea4e42d8b1 (diff)
usb: dwc3: core: define bit 10 of GCTL register
This bit is necessary for implemeting workaround for known issue with some revisions of this core. Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/dwc3/core.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 69c4583933d1..f2693b63b710 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -157,6 +157,7 @@
#define DWC3_GCTL_PRTCAP_OTG 3
#define DWC3_GCTL_CORESOFTRESET (1 << 11)
+#define DWC3_GCTL_SOFITPSYNC (1 << 10)
#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
#define DWC3_GCTL_DISSCRAMBLE (1 << 3)