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authorJyri Sarha <jsarha@ti.com>2014-12-03 16:24:06 +0200
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-12-04 11:17:24 +0200
commitf3b7d0efc6b401c4e06cac45b085ddd56ba28208 (patch)
tree1eaaa1f6e60b91f8e9ca1aa9ff99cea90dc22593 /drivers/video/fbdev
parent39c1b7bf7222a036d1eefbe76d416100904a85b0 (diff)
OMAPDSS: hdmi5: Fix bit field for IEC958_AES2_CON_SOURCE
The bit field for IEC958_AES2_CON_SOURCE is bits 3-0 in HDMI_CORE_FC_AUDSCHNLS2, not imaginary bits 3-4 (reverse order). Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/fbdev')
-rw-r--r--drivers/video/fbdev/omap2/dss/hdmi5_core.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/video/fbdev/omap2/dss/hdmi5_core.c b/drivers/video/fbdev/omap2/dss/hdmi5_core.c
index a71157935e33..a3cfe3d708f7 100644
--- a/drivers/video/fbdev/omap2/dss/hdmi5_core.c
+++ b/drivers/video/fbdev/omap2/dss/hdmi5_core.c
@@ -716,7 +716,7 @@ static void hdmi5_core_audio_config(struct hdmi_core_data *core,
/* Source number */
val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
- REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 4);
+ REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
/* Channel number right 0 */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);