diff options
| author | Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com> | 2009-12-10 14:43:56 -0600 |
|---|---|---|
| committer | Alejandro Gonzalez <alex.gonzalez@digi.com> | 2010-02-12 17:19:45 +0100 |
| commit | 9ba449e22ef33129d1d2e82c30cfcccb922ffc96 (patch) | |
| tree | 5771734209da6c8a9297feb24804f2fce7342183 /drivers/video/mxc | |
| parent | 6bf49f588ac3cfd943bd4bf305bc4949240dfb98 (diff) | |
ENGR00119202: Fix DVFS-PER related bugs.
DVFS-PER needs to make sure that the pixel clock divider is an
even integer.
Added support for pixel clock being sourced from an external clock (PLL3)
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
Diffstat (limited to 'drivers/video/mxc')
| -rw-r--r-- | drivers/video/mxc/mxc_ipuv3_fb.c | 10 | ||||
| -rw-r--r-- | drivers/video/mxc/tve.c | 8 |
2 files changed, 17 insertions, 1 deletions
diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c index 279b9527b4a7..f9b8f6b0f84c 100644 --- a/drivers/video/mxc/mxc_ipuv3_fb.c +++ b/drivers/video/mxc/mxc_ipuv3_fb.c @@ -97,6 +97,7 @@ static unsigned long default_bpp = 16; static bool g_dp_in_use; LIST_HEAD(fb_alloc_list); static struct fb_info *mxcfb_info[3]; +static int ext_clk_used; static uint32_t bpp_to_pixfmt(struct fb_info *fbi) { @@ -328,7 +329,7 @@ static int mxcfb_set_par(struct fb_info *fbi) } if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */ sig_cfg.odd_field_first = true; - if (fbi->var.sync & FB_SYNC_EXT) + if ((fbi->var.sync & FB_SYNC_EXT) || ext_clk_used) sig_cfg.ext_clk = true; if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) sig_cfg.Hsync_pol = true; @@ -1621,10 +1622,17 @@ int mxcfb_setup(char *options) while ((opt = strsep(&options, ",")) != NULL) { if (!*opt) continue; + if (!strncmp(opt, "ext_clk", 7)) { + ext_clk_used = true; + continue; + } else + ext_clk_used = false; + if (!strncmp(opt, "bpp=", 4)) default_bpp = simple_strtoul(opt + 4, NULL, 0); else fb_mode = opt; + } return 0; } diff --git a/drivers/video/mxc/tve.c b/drivers/video/mxc/tve.c index b32110c91128..061d65a7cd20 100644 --- a/drivers/video/mxc/tve.c +++ b/drivers/video/mxc/tve.c @@ -222,6 +222,7 @@ static int tve_setup(int mode) u32 reg; struct clk *pll3_clk; unsigned long pll3_clock_rate = 216000000; + struct clk *ipu_di0_clk; if (tve.cur_mode == mode) return 0; @@ -241,6 +242,13 @@ static int tve_setup(int mode) clk_disable(tve.clk); pll3_clk = clk_get(NULL, "pll3"); + ipu_di0_clk = clk_get(NULL, "ipu_di0_clk"); + if ((clk_get_parent(ipu_di0_clk) == pll3_clk) && + (clk_get_rate(pll3_clk) != pll3_clock_rate)) { + printk(KERN_INFO "Cannot setup TV since display is using PLL3\n"); + return -EINVAL; + } + clk_disable(pll3_clk); clk_set_rate(pll3_clk, pll3_clock_rate); clk_enable(pll3_clk); |