diff options
| author | Ricardo Neri <ricardo.neri@ti.com> | 2013-09-13 15:59:34 +0530 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2013-09-27 09:58:21 +0300 |
| commit | a798eb7ee8c0b852bbca4a4ff44883ca7eac9f58 (patch) | |
| tree | 816d1e31c0e4a1031e74932cb911c763657983cf /drivers/video/omap2 | |
| parent | a7e71262afe1b17bc5523a98a05318f0d9885394 (diff) | |
OMAPDSS: HDMI: OMAP4: Complete register definitions for DPLL
Add missing register definitions for spread spectrum clocking.
Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2')
| -rw-r--r-- | drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h index 469d4366883d..d1a23152680a 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h +++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h @@ -168,6 +168,8 @@ #define PLLCTRL_CFG1 0xC #define PLLCTRL_CFG2 0x10 #define PLLCTRL_CFG3 0x14 +#define PLLCTRL_SSC_CFG1 0x18 +#define PLLCTRL_SSC_CFG2 0x1C #define PLLCTRL_CFG4 0x20 /* HDMI PHY */ |