diff options
author | Xin Xie <xxie@nvidia.com> | 2011-06-28 13:12:48 -0700 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:13 -0800 |
commit | fe1f889383bb4ecd8eb18a830b63e613dd2acdb8 (patch) | |
tree | 03ff1863ac98ab772c9cc542c7887b570f3d17de /drivers/video/tegra/dc/dc.c | |
parent | 02b3b5a58a3f49b0250bccf7a8ae91250591129b (diff) |
video: tegra: dc: fix DSI pclk calculation
BUG 844499
Original-Change-Id: Ib99a921456f4a6e8e3e2d40907a91d492daf4bc0
Reviewed-on: http://git-master/r/38773
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R6dccc88053c055d9e4828d6f4d4e18932f0502f2
Diffstat (limited to 'drivers/video/tegra/dc/dc.c')
-rw-r--r-- | drivers/video/tegra/dc/dc.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 341e52b64e6c..d5d525a5758d 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -681,7 +681,7 @@ static unsigned long tegra_dc_get_emc_rate(struct tegra_dc_win *wins[], int n) for (i = 0; w = wins[i], bw[i] = 0, i < n; i++) { if (!WIN_IS_ENABLED(w)) continue; - bw[i] = dc->mode.pclk * + bw[i] = dc->pixel_clk * (tegra_dc_fmt_bpp(w->fmt) >> BIT_TO_BYTE_SHIFT) * (WIN_USE_V_FILTER(w) ? 2 : 1) / w->out_w * w->w * @@ -1194,14 +1194,14 @@ static int calc_ref_to_sync(struct tegra_dc_mode *mode) #ifdef DEBUG /* return in 1000ths of a Hertz */ -static int calc_refresh(const struct tegra_dc_mode *m) +static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m) { long h_total, v_total, refresh; h_total = m->h_active + m->h_front_porch + m->h_back_porch + m->h_sync_width; v_total = m->v_active + m->v_front_porch + m->v_back_porch + m->v_sync_width; - refresh = m->pclk / h_total; + refresh = dc->pixel_clk / h_total; refresh *= 1000; refresh /= v_total; return refresh; @@ -1311,6 +1311,8 @@ static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div), DC_DISP_DISP_CLOCK_CONTROL); + dc->pixel_clk = dc->mode.pclk; + return 0; } |