diff options
| author | Tom Cherry <tcherry@nvidia.com> | 2013-07-17 18:05:27 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:41:09 -0700 |
| commit | 084344de134aefbca6ddc84035427b218f60aae6 (patch) | |
| tree | 8974ac3d0c92f7c1f3226bdb237f409f7098e63d /drivers/video/tegra/dc/hdmi.c | |
| parent | 052ca0ae17cc32784e95e9762b197d7fa179076f (diff) | |
video: tegra: hdmi: T148 Prod settings
Bug 1250270
Bug 1316334
Change-Id: I3187dd7c890e8aacd1e17a9bb85c4ba871d4aa43
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/250461
(cherry picked from commit adae313395baf9047629162b0380b07abf9c8490)
Reviewed-on: http://git-master/r/261660
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/video/tegra/dc/hdmi.c')
| -rw-r--r-- | drivers/video/tegra/dc/hdmi.c | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/drivers/video/tegra/dc/hdmi.c b/drivers/video/tegra/dc/hdmi.c index 7b340b0c5fb3..1ca6a668fec3 100644 --- a/drivers/video/tegra/dc/hdmi.c +++ b/drivers/video/tegra/dc/hdmi.c @@ -215,17 +215,35 @@ const struct tmds_config tmds_config[] = { }; #elif defined(CONFIG_ARCH_TEGRA_14x_SOC) const struct tmds_config tmds_config[] = { - /* TODO: 480p modes */ - /* TODO: 720p modes */ + { /* 480p modes */ + .pclk = 27000000, + .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | + SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0xF) | + SOR_PLL_TX_REG_LOAD(0), + .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN | + SOR_PLL_TMDS_TERMADJ(0x7) | SOR_PLL_LOADADJ(3), + .pe_current = 0x08080808, + .drive_current = 0x26262626, + }, + { /* 720p modes */ + .pclk = 74250000, + .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | + SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0xF) | + SOR_PLL_TX_REG_LOAD(0), + .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN | + SOR_PLL_TMDS_TERMADJ(0x7) | SOR_PLL_LOADADJ(3), + .pe_current = 0x08080808, + .drive_current = 0x2a2a2a2a, + }, { /* 1080p modes */ .pclk = INT_MAX, .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | - SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(3) | + SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0xF) | SOR_PLL_TX_REG_LOAD(0), .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN | - SOR_PLL_TMDS_TERMADJ(0x6), + SOR_PLL_TMDS_TERMADJ(0x7) | SOR_PLL_LOADADJ(3), .pe_current = 0x08080808, - .drive_current = 0x18181818, + .drive_current = 0x26262626, }, }; #else |