diff options
| author | Aron Wong <awong@nvidia.com> | 2014-02-13 15:07:44 -0800 |
|---|---|---|
| committer | Mitch Luban <mluban@nvidia.com> | 2014-03-05 16:04:55 -0800 |
| commit | 45892368f3fbe361b445aaf5d62ed9bf8a774da9 (patch) | |
| tree | 3bbdeb5d60fb5ea8284fe8e520e350fe042c9aa9 /drivers/video/tegra/dc/hdmi.c | |
| parent | ae173fb2fe3ada9597063a7e49c3fdac994323eb (diff) | |
drivers: video: HDMI prod setting update for T124
Bug 1327251
Update default Ardbeg HDMI pad settings.
PLLD2_KCP set to 0 for all HDMI pixel clocks.
Change-Id: I46392713fcc220663460cd54dd35d06cb3f6f8a7
Signed-off-by: Aron Wong <awong@nvidia.com>
Reviewed-on: http://git-master/r/376296
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/hdmi.c')
| -rw-r--r-- | drivers/video/tegra/dc/hdmi.c | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/drivers/video/tegra/dc/hdmi.c b/drivers/video/tegra/dc/hdmi.c index 7f03027a9555..5b3dca914fd9 100644 --- a/drivers/video/tegra/dc/hdmi.c +++ b/drivers/video/tegra/dc/hdmi.c @@ -137,7 +137,7 @@ const struct tmds_config tmds_config[] = { .drive_current = 0x0f0f0f0f, }, }; -#elif defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC) +#elif defined(CONFIG_ARCH_TEGRA_11x_SOC) const struct tmds_config tmds_config[] = { { /* 480p/576p / 25.2MHz/27MHz modes */ .pclk = 27000000, @@ -182,6 +182,58 @@ const struct tmds_config tmds_config[] = { */ }, }; +#elif defined(CONFIG_ARCH_TEGRA_12x_SOC) +const struct tmds_config tmds_config[] = { + { /* 480p/576p / 25.2MHz/27MHz modes */ + .version = MKDEV(1, 0), + .pclk = 27000000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL_EXT, + .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), + .pe_current = 0x00000000, + .drive_current = 0x1a1a1a1a, + .peak_current = 0x00000000, + .pad_ctls0_mask = 0xfffff0ff, + .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */ + }, + { /* 720p / 74.25MHz modes */ + .version = MKDEV(1, 0), + .pclk = 74250000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL_EXT, + .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), + .pe_current = 0x0f0f0f0f, + .drive_current = 0x1a1a1a1a, + .peak_current = 0x00000000, + .pad_ctls0_mask = 0xfffff0ff, + .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */ + }, + { /* 1080p / 148.5MHz modes */ + .version = MKDEV(1, 0), + .pclk = 148500000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL_EXT, + .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), + .pe_current = 0x0a0a0a0a, + .drive_current = 0x1f1f1f1f, + .peak_current = 0x00000000, + .pad_ctls0_mask = 0xfffff0ff, + .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */ + }, + { /* 225/297MHz modes */ + .version = MKDEV(1, 0), + .pclk = INT_MAX, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL_EXT, + .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) + | SOR_PLL_TMDS_TERM_ENABLE, + .pe_current = 0x00000000, + .drive_current = 0x303f3f3f, /* lane3 needs a slightly lower current */ + .peak_current = 0x040f0f0f, + .pad_ctls0_mask = 0xfffff0ff, + .pad_ctls0_setting = 0x00000600, /* BG_VREF_LEVEL */ + }, +}; #elif defined(CONFIG_ARCH_TEGRA_14x_SOC) const struct tmds_config tmds_config[] = { { /* 480p modes */ |