nvhost: Modularize ACM code

Refactor nvhost_acm.c so that module specific code can be separated from
generic code:

* Module clock and power op descriptions added to channelmap table
  * New module busy/idle interface added
  * 3D clock scaling for Tegra3 moved behind the module busy/idle API
  * 3D power off code moved to 3dctx where it belongs
* Module power on API removed as there were no users
* Get/Set rate moved to Tegra3 specific file

Bug 870791

Change-Id: I2c1612dcadd90046f43f9d81ff790a6d9e7d9804
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit b01476638647e10cfc914da9e0c75996e0e71ae6)
Reviewed-on: http://git-master/r/50280
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Tested-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

3 files changed, 44 insertions, 62 deletions

diff --git a/drivers/video/tegra/host/t20/cdma_t20.c b/drivers/video/tegra/host/t20/cdma_t20.c
index 9413455d4b3b..633d4e700f8c 100644
--- a/drivers/video/tegra/host/t20/cdma_t20.c
+++ b/drivers/video/tegra/host/t20/cdma_t20.c
@@ -137,7 +137,6 @@ static void t20_push_buffer_push_to(struct push_buffer *pb,
 	pb->nvmap[cur/8].client = client;
 	pb->nvmap[cur/8].handle = handle;
 	pb->cur = (cur + 8) & (PUSH_BUFFER_SIZE - 1);
-	/* printk("push_to_push_buffer: op1=%08x; op2=%08x; cur=%x\n", op1, op2, pb->cur); */
 }
 
 /**
@@ -578,7 +577,7 @@ void t20_cdma_timeout_teardown_begin(struct nvhost_cdma *cdma)
 		ch->aperture + HOST1X_CHANNEL_DMACTRL);
 
 	writel(BIT(ch->chid), dev->sync_aperture + HOST1X_SYNC_CH_TEARDOWN);
-	nvhost_module_reset(&ch->mod);
+	nvhost_module_reset(&dev->pdev->dev, &ch->mod);
 
 	cdma->running = false;
 	cdma->torndown = true;
diff --git a/drivers/video/tegra/host/t20/channel_t20.c b/drivers/video/tegra/host/t20/channel_t20.c
index 386682b6f0ed..d06b1e025442 100644
--- a/drivers/video/tegra/host/t20/channel_t20.c
+++ b/drivers/video/tegra/host/t20/channel_t20.c
@@ -24,12 +24,13 @@
 #include "../dev.h"
 #include "../nvhost_hwctx.h"
 #include <trace/events/nvhost.h>
+#include <mach/powergate.h>
 
 #include "hardware_t20.h"
 #include "syncpt_t20.h"
 #include "../dev.h"
 #include "3dctx_t20.h"
-#include "../t30/3dctx_t30.h"
+#include "../3dctx_common.h"
 
 #define NVHOST_NUMCHANNELS (NV_HOST1X_CHANNELS - 1)
 #define NVHOST_CHANNEL_BASE 0
@@ -45,8 +46,7 @@
 #define NVMODMUTEX_DSI       (9)
 #define NV_FIFO_READ_TIMEOUT 200000
 
-static void power_3d(struct nvhost_module *mod, enum nvhost_power_action action);
-
+static void power_off_3d(struct nvhost_module *);
 
 const struct nvhost_channeldesc nvhost_t20_channelmap[] = {
 {
@@ -57,6 +57,10 @@ const struct nvhost_channeldesc nvhost_t20_channelmap[] = {
 			 BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
 			 BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
 	.modulemutexes = BIT(NVMODMUTEX_DISPLAYA) | BIT(NVMODMUTEX_DISPLAYB),
+	.module        = {
+			NVHOST_MODULE_NO_POWERGATING,
+			NVHOST_DEFAULT_POWERDOWN_DELAY,
+			},
 },
 {
 	/* channel 1 */
@@ -65,7 +69,12 @@ const struct nvhost_channeldesc nvhost_t20_channelmap[] = {
 	.waitbases     = BIT(NVWAITBASE_3D),
 	.modulemutexes = BIT(NVMODMUTEX_3D),
 	.class	       = NV_GRAPHICS_3D_CLASS_ID,
-	.power         = power_3d,
+	.module        = {
+			.prepare_poweroff = power_off_3d,
+			.clocks = {{"gr3d", UINT_MAX}, {"emc", UINT_MAX}, {} },
+			.powergate_ids = {TEGRA_POWERGATE_3D, -1},
+			NVHOST_DEFAULT_POWERDOWN_DELAY,
+			},
 },
 {
 	/* channel 2 */
@@ -74,11 +83,22 @@ const struct nvhost_channeldesc nvhost_t20_channelmap[] = {
 	.waitbases     = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
 	.modulemutexes = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
 			 BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
+	.module        = {
+			.clocks = {{"gr2d", UINT_MAX} ,
+					{"epp", UINT_MAX} ,
+					{"emc", UINT_MAX} },
+			NVHOST_MODULE_NO_POWERGATING,
+			.powerdown_delay = 0,
+			}
 },
 {
 	/* channel 3 */
 	.name	 = "isp",
 	.syncpts = 0,
+	.module         = {
+			NVHOST_MODULE_NO_POWERGATING,
+			NVHOST_DEFAULT_POWERDOWN_DELAY,
+			},
 },
 {
 	/* channel 4 */
@@ -89,6 +109,10 @@ const struct nvhost_channeldesc nvhost_t20_channelmap[] = {
 			 BIT(NVSYNCPT_VI_ISP_4),
 	.modulemutexes = BIT(NVMODMUTEX_VI),
 	.exclusive     = true,
+	.module        = {
+			NVHOST_MODULE_NO_POWERGATING,
+			NVHOST_DEFAULT_POWERDOWN_DELAY,
+			}
 },
 {
 	/* channel 5 */
@@ -99,12 +123,21 @@ const struct nvhost_channeldesc nvhost_t20_channelmap[] = {
 	.class	       = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
 	.exclusive     = true,
 	.keepalive     = true,
+	.module        = {
+			.clocks = {{"mpe", UINT_MAX}, {"emc", UINT_MAX}, {} },
+			.powergate_ids = {TEGRA_POWERGATE_MPE, -1},
+			NVHOST_DEFAULT_POWERDOWN_DELAY,
+			},
 },
 {
 	/* channel 6 */
 	.name	       = "dsi",
 	.syncpts       = BIT(NVSYNCPT_DSI),
 	.modulemutexes = BIT(NVMODMUTEX_DSI),
+	.module        = {
+			NVHOST_MODULE_NO_POWERGATING,
+			NVHOST_DEFAULT_POWERDOWN_DELAY,
+			},
 }};
 
 static inline void __iomem *t20_channel_aperture(void __iomem *p, int ndx)
@@ -164,8 +197,8 @@ static int t20_channel_submit(struct nvhost_channel *channel,
 
 	/* keep module powered */
 	nvhost_module_busy(&channel->mod);
-	if (strcmp(channel->mod.name, "gr3d") == 0)
-		module3d_notify_busy();
+	if (channel->mod.desc->busy)
+		channel->mod.desc->busy(&channel->mod);
 
 	/* before error checks, return current max */
 	*syncpt_value = nvhost_syncpt_read_max(sp, syncpt_id);
@@ -317,61 +350,9 @@ static int t20_channel_submit(struct nvhost_channel *channel,
 	return 0;
 }
 
-static void power_3d(struct nvhost_module *mod, enum nvhost_power_action action)
+void power_off_3d(struct nvhost_module *mod)
 {
-	struct nvhost_channel *ch = container_of(mod, struct nvhost_channel, mod);
-	struct nvhost_hwctx *hwctx_to_save;
-	DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
-	u32 syncpt_incrs, syncpt_val;
-	int err;
-	void *ref;
-
-	if (action != NVHOST_POWER_ACTION_OFF)
-		return;
-
-	mutex_lock(&ch->submitlock);
-	hwctx_to_save = ch->cur_ctx;
-	if (!hwctx_to_save) {
-		mutex_unlock(&ch->submitlock);
-		return;
-	}
-
-	if (strcmp(mod->name, "gr3d") == 0)
-		module3d_notify_busy();
-
-	err = nvhost_cdma_begin(&ch->cdma, hwctx_to_save->timeout);
-	if (err) {
-		mutex_unlock(&ch->submitlock);
-		return;
-	}
-
-	hwctx_to_save->valid = true;
-	ch->ctxhandler.get(hwctx_to_save);
-	ch->cur_ctx = NULL;
-
-	syncpt_incrs = hwctx_to_save->save_incrs;
-	syncpt_val = nvhost_syncpt_incr_max(&ch->dev->syncpt,
-					NVSYNCPT_3D, syncpt_incrs);
-
-	ch->ctxhandler.save_push(&ch->cdma, hwctx_to_save);
-	nvhost_cdma_end(&ch->cdma, ch->dev->nvmap, NVSYNCPT_3D, syncpt_val,
-			NULL, 0, hwctx_to_save->timeout);
-
-	nvhost_intr_add_action(&ch->dev->intr, NVSYNCPT_3D,
-			syncpt_val - syncpt_incrs + hwctx_to_save->save_thresh,
-			NVHOST_INTR_ACTION_CTXSAVE, hwctx_to_save, NULL);
-
-	nvhost_intr_add_action(&ch->dev->intr, NVSYNCPT_3D, syncpt_val,
-			NVHOST_INTR_ACTION_WAKEUP, &wq, &ref);
-	wait_event(wq,
-		nvhost_syncpt_min_cmp(&ch->dev->syncpt,
-				NVSYNCPT_3D, syncpt_val));
-
-	nvhost_intr_put_ref(&ch->dev->intr, ref);
-
-	nvhost_cdma_update(&ch->cdma);
-
-	mutex_unlock(&ch->submitlock);
+	nvhost_3dctx_prepare_power_off(mod);
 }
 
 static int t20_channel_read_3d_reg(
diff --git a/drivers/video/tegra/host/t20/t20.h b/drivers/video/tegra/host/t20/t20.h
index 8a8426c740d1..406841092f01 100644
--- a/drivers/video/tegra/host/t20/t20.h
+++ b/drivers/video/tegra/host/t20/t20.h
@@ -22,6 +22,8 @@
 #ifndef _NVHOST_T20_H_
 #define _NVHOST_T20_H_
 
+struct nvhost_master;
+
 int nvhost_init_t20_channel_support(struct nvhost_master *);
 int nvhost_init_t20_cdma_support(struct nvhost_master *);
 int nvhost_init_t20_debug_support(struct nvhost_master *);