diff options
| author | Ondrej Zary <linux@rainbow-software.org> | 2011-03-01 19:18:27 +0000 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2011-03-22 15:49:53 +0900 |
| commit | 3827d10ed4278323b75bf25d09c146c050519254 (patch) | |
| tree | db1061c67573cf888f47349110fbfb5c5d2b3bd2 /drivers/video | |
| parent | 5694f9ce5801d58bfc1b011592a5e460cc0a274b (diff) | |
s3fb: fix 15/16bpp modes with over 115MHz pixclocks on 86C365 Trio3D
Enable pixel multiplexing in 15/16bpp modes when pixclock is over 115MHz
on Trio3D (86C365) cards to fix artifacts on the left side of screen.
Signed-off-by: Ondrej Zary <linux@rainbow-software.org>
Acked-by: Ondrej Zajicek <santiago@crfreenet.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/s3fb.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index be12145681f6..7b8fdc6d9d55 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c @@ -675,6 +675,15 @@ static int s3fb_set_par(struct fb_info *info) svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); + } else if (par->chip == CHIP_365_TRIO3D) { + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + if (info->var.pixclock > 8695) { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); + hmul = 2; + } else { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); + multiplex = 1; + } } else { svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); @@ -691,6 +700,15 @@ static int s3fb_set_par(struct fb_info *info) svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); + } else if (par->chip == CHIP_365_TRIO3D) { + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + if (info->var.pixclock > 8695) { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); + hmul = 2; + } else { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); + multiplex = 1; + } } else { svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); |