ARM: tegra: Verify PHY clock valid before clearing USB_SUSP_CLR bit

When enabling the external ULPI PHY, the clock from the PHY must be
valid before the USB_SUSP_CLR bit is cleared in the USB2 controller
interface register.  If the clock from the PHY is not valid when
this bit is cleared, the AHB clock to the host controller may be
stopped, preventing any access to the host controller.

Replace hard-coded delay with poll for USB_PHY_CLK_VALID bit.
Signed-off-by: Nathan Connell <w14185@motorola.com>

Change-Id: I24fa7575641f20ffdba7737776a81ba453f54395
Signed-off-by: Nathan Connell <w14185@motorola.com>

0 files changed, 0 insertions, 0 deletions