diff options
| author | Jon Mayo <jmayo@nvidia.com> | 2011-02-10 15:35:38 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:55:07 -0700 |
| commit | 8d670def28a3fea81add55dffbe30fec5d4e98bf (patch) | |
| tree | 861b70795347a9e5cadd4e684ce2df1458e619a5 /drivers/video | |
| parent | fd0fad5517e7f50e08a6d4de8fe5fb07e3f7ea43 (diff) | |
ARM: tegra: dc: hdmi drive strength changes
use pixel clock to configure HDMI interface signaling properties.
These options are different depending on which SoC.
Bug 786961 Bug 795251
Original-Change-Id: Ic898e87134cbac0fe5723242febdf46bc5b72d32
Reviewed-on: http://git-master/r/19176
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Change-Id: I98d68da65e590a0eb5cf7fac166d05e0c531bd5f
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/tegra/dc/hdmi.c | 47 |
1 files changed, 46 insertions, 1 deletions
diff --git a/drivers/video/tegra/dc/hdmi.c b/drivers/video/tegra/dc/hdmi.c index d5019eb04aba..f7f1b6467d7b 100644 --- a/drivers/video/tegra/dc/hdmi.c +++ b/drivers/video/tegra/dc/hdmi.c @@ -211,7 +211,52 @@ struct tdms_config { u32 drive_current; }; -#ifdef CONFIG_ARCH_TEGRA_2x_SOC +#ifdef CONFIG_ARCH_TEGRA_3x_SOC +const struct tdms_config tdms_config[] = { + { /* 480p modes */ + .pclk = 27000000, + .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL | + SOR_PLL_VCOCAP(0) | SOR_PLL_TX_REG_LOAD(0), + .pll1 = SOR_PLL_TMDS_TERM_ENABLE, + .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | + PE_CURRENT1(PE_CURRENT_0_0_mA) | + PE_CURRENT2(PE_CURRENT_0_0_mA) | + PE_CURRENT3(PE_CURRENT_0_0_mA), + .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | + DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | + DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | + DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), + }, + { /* 720p modes */ + .pclk = 74250000, + .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL | + SOR_PLL_VCOCAP(1) | SOR_PLL_TX_REG_LOAD(0), + .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, + .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | + PE_CURRENT1(PE_CURRENT_5_0_mA) | + PE_CURRENT2(PE_CURRENT_5_0_mA) | + PE_CURRENT3(PE_CURRENT_5_0_mA), + .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | + DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | + DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | + DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), + }, + { /* 1080p modes */ + .pclk = INT_MAX, + .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | SOR_PLL_RESISTORSEL | + SOR_PLL_VCOCAP(3) | SOR_PLL_TX_REG_LOAD(0), + .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, + .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | + PE_CURRENT1(PE_CURRENT_5_0_mA) | + PE_CURRENT2(PE_CURRENT_5_0_mA) | + PE_CURRENT3(PE_CURRENT_5_0_mA), + .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | + DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | + DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | + DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), + }, +}; +#else /* CONFIG_ARCH_TEGRA_2x_SOC */ const struct tdms_config tdms_config[] = { { /* 480p modes */ .pclk = 27000000, |