diff options
| author | David Pu <dpu@nvidia.com> | 2016-01-26 11:21:06 -0800 |
|---|---|---|
| committer | Winnie Hsu <whsu@nvidia.com> | 2018-03-14 14:27:23 -0700 |
| commit | 1357daf84c6e99b32c50ed39a524871d003d1886 (patch) | |
| tree | b103070629f61e8e3ac61f5cab0ab442135cf82a /drivers/video | |
| parent | 9d09b31470a2714817375f86d9e56ffb1b617739 (diff) | |
video: tegra: sor: set drive current for lane4
drive current for LANE4 was not set if configured as 24bpp lvds out.
fix it by programming proper drive current register if using 24bpp out.
Bug 1724122
Change-Id: Ie2ad71ace0b4f247e007e671be828230545b15f6
Signed-off-by: David Pu <dpu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1544691
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Wayne Wang (SW-TEGRA) <waywang@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/tegra/dc/sor.c | 6 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/sor_regs.h | 3 |
2 files changed, 7 insertions, 2 deletions
diff --git a/drivers/video/tegra/dc/sor.c b/drivers/video/tegra/dc/sor.c index e5fe66be55d0..f4992eced400 100644 --- a/drivers/video/tegra/dc/sor.c +++ b/drivers/video/tegra/dc/sor.c @@ -1,7 +1,7 @@ /* * drivers/video/tegra/dc/sor.c * - * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -186,6 +186,7 @@ static int dbg_sor_show(struct seq_file *s, void *unused) DUMP_REG(NV_SOR_DC(0)); DUMP_REG(NV_SOR_DC(1)); DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0)); + DUMP_REG(NV_SOR_LANE4_DRIVE_CURRENT(0)); DUMP_REG(NV_SOR_PR(0)); DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0)); DUMP_REG(NV_SOR_POSTCURSOR(0)); @@ -1230,6 +1231,9 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor, tegra_sor_writel(sor, NV_SOR_LVDS, reg_val); tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), 0x40404040); + if (!conforming && (sor->dc->pdata->default_out->depth == 24)) + tegra_sor_writel(sor, NV_SOR_LANE4_DRIVE_CURRENT(sor->portnum), + 0x40); #if 0 tegra_sor_write_field(sor, NV_SOR_LVDS, diff --git a/drivers/video/tegra/dc/sor_regs.h b/drivers/video/tegra/dc/sor_regs.h index cbf4b94c1664..8080e2925d82 100644 --- a/drivers/video/tegra/dc/sor_regs.h +++ b/drivers/video/tegra/dc/sor_regs.h @@ -1,7 +1,7 @@ /* * drivers/video/tegra/dc/sor_regs.h * - * Copyright (c) 2011-2013, NVIDIA CORPORATION, All rights reserved. + * Copyright (c) 2011-2017, NVIDIA CORPORATION, All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -611,6 +611,7 @@ #define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2 (43) #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3 (51) #define NV_SOR_LANE_DRIVE_CURRENT(i) (0x4e + (i)) +#define NV_SOR_LANE4_DRIVE_CURRENT(i) (0x50 + (i)) #define NV_SOR_PR(i) (0x52 + (i)) #define NV_SOR_PR_LANE3_DP_LANE3_SHIFT (24) #define NV_SOR_PR_LANE3_DP_LANE3_MASK (0xff << 24) |