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authorAlexander Shiyan <shc_work@mail.ru>2014-02-22 11:29:51 +0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-02-28 15:27:09 -0800
commitfc945d6eb70ebf29532b94ae309c0d4c6d609c3c (patch)
tree736db6b4c35b0b7d7e2c4cb61b7ea7e61cb181b0 /drivers/w1/masters/mxc_w1.c
parent18fd9e359f2515286ae7c7ac8fd4362675c8eb43 (diff)
w1: mxc_w1: Enable driver compilation with COMPILE_TEST
This helps increasing build testing coverage. To do this, __raw_{read,write}b() functions was be replaced with simple {read,write}b() variants. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/w1/masters/mxc_w1.c')
-rw-r--r--drivers/w1/masters/mxc_w1.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index 8e3de6aa88e8..67b067a3e2ab 100644
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -53,10 +53,10 @@ static u8 mxc_w1_ds2_reset_bus(void *data)
unsigned int timeout_cnt = 0;
struct mxc_w1_device *dev = data;
- __raw_writeb(MXC_W1_CONTROL_RPP, (dev->regs + MXC_W1_CONTROL));
+ writeb(MXC_W1_CONTROL_RPP, (dev->regs + MXC_W1_CONTROL));
while (1) {
- reg_val = __raw_readb(dev->regs + MXC_W1_CONTROL);
+ reg_val = readb(dev->regs + MXC_W1_CONTROL);
if (!(reg_val & MXC_W1_CONTROL_RPP) ||
timeout_cnt > MXC_W1_RESET_TIMEOUT)
@@ -82,16 +82,16 @@ static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
* datasheet.
*/
- __raw_writeb(MXC_W1_CONTROL_WR(bit), ctrl_addr);
+ writeb(MXC_W1_CONTROL_WR(bit), ctrl_addr);
while (timeout_cnt--) {
- if (!(__raw_readb(ctrl_addr) & MXC_W1_CONTROL_WR(bit)))
+ if (!(readb(ctrl_addr) & MXC_W1_CONTROL_WR(bit)))
break;
udelay(1);
}
- return !!(__raw_readb(ctrl_addr) & MXC_W1_CONTROL_RDST);
+ return !!(readb(ctrl_addr) & MXC_W1_CONTROL_RDST);
}
static int mxc_w1_probe(struct platform_device *pdev)
@@ -131,7 +131,7 @@ static int mxc_w1_probe(struct platform_device *pdev)
if (err)
return err;
- __raw_writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
+ writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
mdev->bus_master.data = mdev;
mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;