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authorAnson Huang <b20788@freescale.com>2011-11-14 20:31:30 +0800
committerJason Liu <r64343@freescale.com>2012-07-20 13:17:47 +0800
commit9106da8ccd35ef5385b966977cd6482d215510b2 (patch)
treeb3f44b9c21d18c01d144ef3f56822a0c3b94ea06 /drivers/watchdog
parentc343cba44bc755231c70800aefd4d5d3143b0e52 (diff)
ENGR00162115 [WDOG]Should suspend timer in LPM
We should set the WDOG timer to suspend in low power mode, or when system suspend, wdog will continue to run, and reset the system. This WCR_WDZST is a write once-only register. Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'drivers/watchdog')
-rw-r--r--drivers/watchdog/imx2_wdt.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index 86f7cac1026c..ad2a40fefc6c 100644
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -41,6 +41,7 @@
#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
+#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
#define IMX2_WDT_WSR 0x02 /* Service Register */
#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
@@ -85,6 +86,8 @@ static inline void imx2_wdt_setup(void)
{
u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
+ /* Suspend watch dog timer in low power mode, write once-only */
+ val |= IMX2_WDT_WCR_WDZST;
/* Strip the old watchdog Time-Out value */
val &= ~IMX2_WDT_WCR_WT;
/* Generate reset if WDOG times out */