diff options
| author | Gabor Juhos <juhosg@openwrt.org> | 2011-12-23 19:25:42 +0100 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2012-01-06 15:27:51 +0100 |
| commit | 86955e2bcb320bf8f271443cb7b03896fc3cbd67 (patch) | |
| tree | 864d9b8cd1e09a266df38b4970474823b794b013 /drivers/watchdog | |
| parent | 60daac4a9084d5a6216443f428d0060c42eb44ff (diff) | |
watchdog: ath79_wdt: flush register writes
The watchdog register writes required to have a flush
in order to commit the values to the register. Without
the flush, the driver not function correctly on AR934X
SoCs.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers/watchdog')
| -rw-r--r-- | drivers/watchdog/ath79_wdt.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/watchdog/ath79_wdt.c b/drivers/watchdog/ath79_wdt.c index 725c84bfdd76..9db808349f8b 100644 --- a/drivers/watchdog/ath79_wdt.c +++ b/drivers/watchdog/ath79_wdt.c @@ -68,17 +68,23 @@ static int max_timeout; static inline void ath79_wdt_keepalive(void) { ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout); + /* flush write */ + ath79_reset_rr(AR71XX_RESET_REG_WDOG); } static inline void ath79_wdt_enable(void) { ath79_wdt_keepalive(); ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR); + /* flush write */ + ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL); } static inline void ath79_wdt_disable(void) { ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE); + /* flush write */ + ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL); } static int ath79_wdt_set_timeout(int val) |