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authorAnson Huang <b20788@freescale.com>2011-11-14 20:31:30 +0800
committerJason Liu <r64343@freescale.com>2012-01-09 21:06:30 +0800
commit0d41026af160e8d231e6fec1b6ea87af33d27b8d (patch)
tree7814472a63989fb35a398c4245cd10704f1fd201 /drivers/watchdog
parent40ec24936e8bc1b3b0c713368deee1e8325b285e (diff)
ENGR00162115 [WDOG]Should suspend timer in LPM
We should set the WDOG timer to suspend in low power mode, or when system suspend, wdog will continue to run, and reset the system. This WCR_WDZST is a write once-only register. Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'drivers/watchdog')
-rw-r--r--drivers/watchdog/imx2_wdt.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index 86f7cac1026c..ad2a40fefc6c 100644
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -41,6 +41,7 @@
#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
+#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
#define IMX2_WDT_WSR 0x02 /* Service Register */
#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
@@ -85,6 +86,8 @@ static inline void imx2_wdt_setup(void)
{
u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
+ /* Suspend watch dog timer in low power mode, write once-only */
+ val |= IMX2_WDT_WCR_WDZST;
/* Strip the old watchdog Time-Out value */
val &= ~IMX2_WDT_WCR_WT;
/* Generate reset if WDOG times out */