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authorKevin Hilman <khilman@linaro.org>2015-06-11 16:36:32 -0700
committerKevin Hilman <khilman@linaro.org>2015-06-11 16:36:32 -0700
commit2879e43f09122f8b3ef5456e3d7e48716b086e60 (patch)
tree0399726ae8acb415504a8b4878f341b643ad3bf4 /drivers
parent4d48614ec45aa20d6a2cb7d2eb1368d7641c747d (diff)
parent436bbc12452c23b9e7385f3fcabc82fdd387a55a (diff)
Merge tag 'omap-for-v4.2/soc-pt1-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Omap hwmod changes for v4.2 via Paul Walmsley <paul@pwsan.com>: Several OMAP2+ hwmod changes for v4.2. One patch cleans up a nasty interaction between the OMAP GPMC and the hwmod code when debugging is enabled. IP block integration data has been added for the AM43xx EMIF RAM controller. There's also a fix for the omap-aes driver when used in QEMU. And finally, some changes to the OMAP3 hwmod code to support the use of the security IP blocks (AES and SHA) on GP devices, or when they've specifically been enabled in the DT data. Basic build, boot, and power management test results are here: http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.2/20150601192349/ * tag 'omap-for-v4.2/soc-pt1-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP3: Fix crypto support for HS devices ARM: OMAP2+: Return correct error values from device and hwmod ARM: OMAP: AM43xx hwmod: Add data for am43xx emif hwmod memory: omap-gpmc: Add Kconfig option for debug
Diffstat (limited to 'drivers')
-rw-r--r--drivers/memory/Kconfig8
-rw-r--r--drivers/memory/omap-gpmc.c6
2 files changed, 11 insertions, 3 deletions
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 868036f70f8f..8406c668ecdc 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -49,6 +49,14 @@ config OMAP_GPMC
interfacing to a variety of asynchronous as well as synchronous
memory drives like NOR, NAND, OneNAND, SRAM.
+config OMAP_GPMC_DEBUG
+ bool
+ depends on OMAP_GPMC
+ help
+ Enables verbose debugging mostly to decode the bootloader provided
+ timings. Enable this during development to configure devices
+ connected to the GPMC bus.
+
config MVEBU_DEVBUS
bool "Marvell EBU Device Bus Controller"
default y
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index c94ea0d68746..8911e51d410a 100644
--- a/drivers/memory/omap-gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -403,7 +403,7 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
p->cycle2cyclediffcsen);
}
-#ifdef DEBUG
+#ifdef CONFIG_OMAP_GPMC_DEBUG
/**
* get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
* @cs: Chip Select Region
@@ -612,7 +612,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max
}
l = gpmc_cs_read_reg(cs, reg);
-#ifdef DEBUG
+#ifdef CONFIG_OMAP_GPMC_DEBUG
pr_info(
"GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
@@ -767,7 +767,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
clk_activation, GPMC_CD_FCLK);
-#ifdef DEBUG
+#ifdef CONFIG_OMAP_GPMC_DEBUG
pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
cs, (div * gpmc_get_fclk_period()) / 1000, div);
#endif