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authorLaxman Dewangan <ldewangan@nvidia.com>2012-03-27 18:57:11 +0530
committerSimone Willett <swillett@nvidia.com>2012-04-18 18:36:31 -0700
commit28adfa50e474f5a35c720e043575d9f66252de7d (patch)
treed7c027dece168b032234255ca22524e514236fba /drivers
parent3069e6a7179f77469274112a94d8556445ee63e4 (diff)
i2c: tegra: support for I2C_M_NOSTART protocol mangling
Adding support for protocol mangling I2C_M_NOSTART. Change-Id: I6cc0c96b3c374d452ea886a0f983dc5d31c4575c Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/92573 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/i2c/busses/i2c-tegra.c30
1 files changed, 26 insertions, 4 deletions
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index a4c1e0d82939..25ad6dca3884 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -106,13 +106,26 @@
#define I2C_HEADER_10BIT_ADDR (1<<18)
#define I2C_HEADER_IE_ENABLE (1<<17)
#define I2C_HEADER_REPEAT_START (1<<16)
+#define I2C_HEADER_CONTINUE_XFER (1<<15)
#define I2C_HEADER_MASTER_ADDR_SHIFT 12
#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
#define SL_ADDR1(addr) (addr & 0xff)
#define SL_ADDR2(addr) ((addr >> 8) & 0xff)
+/*
+ * msg_end_type: The bus control which need to be send at end of transfer.
+ * @MSG_END_STOP: Send stop pulse at end of transfer.
+ * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
+ * @MSG_END_CONTINUE: The following on message is coming and so do not send
+ * stop or repeat start.
+ */
+enum msg_end_type {
+ MSG_END_STOP,
+ MSG_END_REPEAT_START,
+ MSG_END_CONTINUE,
+};
struct tegra_i2c_dev;
@@ -621,7 +634,7 @@ err:
}
static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
- struct i2c_msg *msg, int stop)
+ struct i2c_msg *msg, enum msg_end_type end_state)
{
struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
u32 int_mask;
@@ -654,8 +667,11 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
i2c_writel(i2c_dev, i2c_dev->payload_size, I2C_TX_FIFO);
i2c_dev->io_header = I2C_HEADER_IE_ENABLE;
- if (!stop)
+ if (end_state == MSG_END_CONTINUE)
+ i2c_dev->io_header |= I2C_HEADER_CONTINUE_XFER;
+ else if (end_state == MSG_END_REPEAT_START)
i2c_dev->io_header |= I2C_HEADER_REPEAT_START;
+
if (msg->flags & I2C_M_TEN) {
i2c_dev->io_header |= msg->addr;
i2c_dev->io_header |= I2C_HEADER_10BIT_ADDR;
@@ -772,8 +788,14 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
tegra_i2c_clock_enable(i2c_dev);
for (i = 0; i < num; i++) {
- int stop = (i == (num - 1)) ? 1 : 0;
- ret = tegra_i2c_xfer_msg(i2c_bus, &msgs[i], stop);
+ enum msg_end_type end_type = MSG_END_STOP;
+ if (i < (num - 1)) {
+ if (msgs[i + 1].flags & I2C_M_NOSTART)
+ end_type = MSG_END_CONTINUE;
+ else
+ end_type = MSG_END_REPEAT_START;
+ }
+ ret = tegra_i2c_xfer_msg(i2c_bus, &msgs[i], end_type);
if (ret)
break;
}