diff options
| author | Diwakar Tundlam <dtundlam@nvidia.com> | 2014-05-05 16:10:57 -0700 |
|---|---|---|
| committer | Riham Haidar <rhaidar@nvidia.com> | 2014-05-07 12:10:44 -0700 |
| commit | 5adedff5b2f46b07c01286bebbad12c17f7a47bf (patch) | |
| tree | 2b3ae31ef3f8049177db9b959db5a5d7ca084a72 /drivers | |
| parent | a5f6618850714d1fa66586e1ad629642b3b7ed3d (diff) | |
arm: tegra: thermal: clean up fuse check apis
Allow fuse check api to be called only to check the fuse revision.
Bug 1429685
Change-Id: I0370f237c4562814af0f41a162bccff2b3db5371
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/405474
Reviewed-on: http://git-master/r/405990
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/misc/tegra-fuse/tegra11x_fuse_offsets.h | 52 | ||||
| -rw-r--r-- | drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h | 8 |
2 files changed, 32 insertions, 28 deletions
diff --git a/drivers/misc/tegra-fuse/tegra11x_fuse_offsets.h b/drivers/misc/tegra-fuse/tegra11x_fuse_offsets.h index 38495300dc3d..1507d845ea07 100644 --- a/drivers/misc/tegra-fuse/tegra11x_fuse_offsets.h +++ b/drivers/misc/tegra-fuse/tegra11x_fuse_offsets.h @@ -229,19 +229,21 @@ int tegra_fuse_calib_base_get_cp(u32 *base_cp, s32 *shifted_cp) s32 cp; u32 val = tegra_fuse_readl(FUSE_VSENSOR_CALIB_0); - *base_cp = (((val) & - (FUSE_BASE_CP_MASK << FUSE_BASE_CP_SHIFT)) - >> FUSE_BASE_CP_SHIFT); - if (!(*base_cp)) { - pr_err("soctherm: ERROR: Improper FUSE. SOC_THERM disabled.\n"); + if (!val) return -EINVAL; - } - cp = (((val) & - (FUSE_SHIFT_CP_MASK << FUSE_SHIFT_CP_SHIFT)) - >> FUSE_SHIFT_CP_SHIFT); - *shifted_cp = ((s32)(cp) << - (32 - FUSE_SHIFT_CP_BITS) >> - (32 - FUSE_SHIFT_CP_BITS)); + + if (base_cp) + *base_cp = (((val) & (FUSE_BASE_CP_MASK + << FUSE_BASE_CP_SHIFT)) + >> FUSE_BASE_CP_SHIFT); + + cp = (((val) & (FUSE_SHIFT_CP_MASK + << FUSE_SHIFT_CP_SHIFT)) + >> FUSE_SHIFT_CP_SHIFT); + if (shifted_cp) + *shifted_cp = ((s32)(cp) + << (32 - FUSE_SHIFT_CP_BITS) + >> (32 - FUSE_SHIFT_CP_BITS)); return 0; } @@ -250,19 +252,21 @@ int tegra_fuse_calib_base_get_ft(u32 *base_ft, s32 *shifted_ft) s32 ft; u32 val = tegra_fuse_readl(FUSE_VSENSOR_CALIB_0); - *base_ft = (((val) & - (FUSE_BASE_FT_MASK << FUSE_BASE_FT_SHIFT)) - >> FUSE_BASE_FT_SHIFT); - if (!(*base_ft)) { - pr_err("soctherm: ERROR: Improper FUSE. SOC_THERM disabled.\n"); + if (!val) return -EINVAL; - } - ft = (((val) & - (FUSE_SHIFT_FT_MASK << FUSE_SHIFT_FT_SHIFT)) - >> FUSE_SHIFT_FT_SHIFT); - *shifted_ft = ((s32)(ft) << - (32 - FUSE_SHIFT_FT_BITS) >> - (32 - FUSE_SHIFT_FT_BITS)); + + if (base_ft) + *base_ft = (((val) & (FUSE_BASE_FT_MASK + << FUSE_BASE_FT_SHIFT)) + >> FUSE_BASE_FT_SHIFT); + + ft = (((val) & (FUSE_SHIFT_FT_MASK + << FUSE_SHIFT_FT_SHIFT)) + >> FUSE_SHIFT_FT_SHIFT); + if (shifted_ft) + *shifted_ft = ((s32)(ft) << + (32 - FUSE_SHIFT_FT_BITS) >> + (32 - FUSE_SHIFT_FT_BITS)); return 0; } diff --git a/drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h b/drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h index 3d54bb888f20..432a6d26d35c 100644 --- a/drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h +++ b/drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h @@ -345,8 +345,8 @@ int tegra_fuse_calib_base_get_cp(u32 *base_cp, s32 *shifted_cp) if (base_cp) *base_cp = (((val) & (FUSE_BASE_CP_MASK - << FUSE_BASE_CP_SHIFT)) - >> FUSE_BASE_CP_SHIFT); + << FUSE_BASE_CP_SHIFT)) + >> FUSE_BASE_CP_SHIFT); val = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0); cp = (((val) & (FUSE_SHIFT_CP_MASK @@ -387,8 +387,8 @@ int tegra_fuse_calib_base_get_ft(u32 *base_ft, s32 *shifted_ft) if (base_ft) *base_ft = (((val) & (FUSE_BASE_FT_MASK - << FUSE_BASE_FT_SHIFT)) - >> FUSE_BASE_FT_SHIFT); + << FUSE_BASE_FT_SHIFT)) + >> FUSE_BASE_FT_SHIFT); ft_or_cp2 = (((val) & (FUSE_SHIFT_FT_MASK << FUSE_SHIFT_FT_SHIFT)) |