video: tegra: host: Replace magic numbers with constants

Replace magic numbers with constants throughout the code base.

Change-Id: If6071f3ee95078d7b631a300b241ebf6522ef68a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/66795
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

14 files changed, 275 insertions, 198 deletions

diff --git a/drivers/video/tegra/host/3d_common.h b/drivers/video/tegra/host/3d_common.h
new file mode 100644
index 000000000000..afac4f2b3e3e
--- /dev/null
+++ b/drivers/video/tegra/host/3d_common.h
@@ -0,0 +1,35 @@
+/*
+ * drivers/video/tegra/host/t30/3dctx_t30.h
+ *
+ * Tegra Graphics Host Context Switching for Tegra3
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __NVHOST_3D_T30_H
+#define __NVHOST_3D_T30_H
+
+/* Registers of 3D unit */
+
+#define AR3D_PSEQ_QUAD_ID 0x545
+#define AR3D_DW_MEMORY_OUTPUT_ADDRESS 0x904
+#define AR3D_DW_MEMORY_OUTPUT_DATA 0x905
+#define AR3D_GSHIM_WRITE_MASK 0xb00
+#define AR3D_GSHIM_READ_SELECT 0xb01
+#define AR3D_GLOBAL_MEMORY_OUTPUT_READS 0xe40
+
+#endif
diff --git a/drivers/video/tegra/host/3dctx_common.c b/drivers/video/tegra/host/3dctx_common.c
index e7673c54e31a..21422eb495e1 100644
--- a/drivers/video/tegra/host/3dctx_common.c
+++ b/drivers/video/tegra/host/3dctx_common.c
@@ -30,6 +30,7 @@
 #include "t20/syncpt_t20.h"
 #include "nvhost_hwctx.h"
 #include "dev.h"
+#include "3d_common.h"
 
 unsigned int nvhost_3dctx_restore_size;
 unsigned int nvhost_3dctx_restore_incrs;
@@ -49,7 +50,7 @@ void nvhost_3dctx_restore_begin(u32 *ptr)
 	/* set class to 3D */
 	ptr[2] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
 	/* program PSEQ_QUAD_ID */
-	ptr[3] = nvhost_opcode_imm(0x545, 0);
+	ptr[3] = nvhost_opcode_imm(AR3D_PSEQ_QUAD_ID, 0);
 }
 
 void nvhost_3dctx_restore_direct(u32 *ptr, u32 start_reg, u32 count)
diff --git a/drivers/video/tegra/host/debug.h b/drivers/video/tegra/host/debug.h
index 9dd3a1995478..874d5c87d57b 100644
--- a/drivers/video/tegra/host/debug.h
+++ b/drivers/video/tegra/host/debug.h
@@ -43,6 +43,7 @@ static inline void write_to_printk(void *ctx, const char* str, size_t len)
 
 void nvhost_debug_output(struct output *o, const char* fmt, ...);
 
+extern pid_t nvhost_debug_null_kickoff_pid;
 extern pid_t nvhost_debug_force_timeout_pid;
 extern u32 nvhost_debug_force_timeout_val;
 extern u32 nvhost_debug_force_timeout_channel;
diff --git a/drivers/video/tegra/host/t20/3dctx_t20.c b/drivers/video/tegra/host/t20/3dctx_t20.c
index d0609fb61976..44bfd6dacb04 100644
--- a/drivers/video/tegra/host/t20/3dctx_t20.c
+++ b/drivers/video/tegra/host/t20/3dctx_t20.c
@@ -22,6 +22,7 @@
 
 #include "../nvhost_hwctx.h"
 #include "../dev.h"
+#include "channel_t20.h"
 #include "hardware_t20.h"
 #include "syncpt_t20.h"
 #include "../3dctx_common.h"
@@ -353,7 +354,7 @@ int __init t20_nvhost_3dctx_handler_init(struct nvhost_hwctx_handler *h)
 
 	setup_save(NULL);
 
-	nvhost_3dctx_save_buf = nvmap_alloc(nvmap, save_size * 4, 32,
+	nvhost_3dctx_save_buf = nvmap_alloc(nvmap, save_size * sizeof(u32), 32,
 				NVMAP_HANDLE_WRITE_COMBINE);
 	if (IS_ERR(nvhost_3dctx_save_buf)) {
 		int err = PTR_ERR(nvhost_3dctx_save_buf);
diff --git a/drivers/video/tegra/host/t20/cdma_t20.c b/drivers/video/tegra/host/t20/cdma_t20.c
index c034bdf90bbc..a7bb45152b1b 100644
--- a/drivers/video/tegra/host/t20/cdma_t20.c
+++ b/drivers/video/tegra/host/t20/cdma_t20.c
@@ -26,6 +26,14 @@
 
 #include "hardware_t20.h"
 #include "syncpt_t20.h"
+#include "cdma_t20.h"
+
+static inline u32 host1x_channel_dmactrl(int stop, int get_rst, int init_get)
+{
+	return HOST1X_CREATE(CHANNEL_DMACTRL, DMASTOP, stop)
+			| HOST1X_CREATE(CHANNEL_DMACTRL, DMAGETRST, get_rst)
+			| HOST1X_CREATE(CHANNEL_DMACTRL, DMAINITGET, init_get);
+}
 
 static void t20_cdma_timeout_handler(struct work_struct *work);
 
@@ -395,7 +403,7 @@ static void t20_cdma_start(struct nvhost_cdma *cdma)
 	BUG_ON(!cdma_pb_op(cdma).putptr);
 	cdma->last_put = cdma_pb_op(cdma).putptr(&cdma->push_buffer);
 
-	writel(nvhost_channel_dmactrl(true, false, false),
+	writel(host1x_channel_dmactrl(true, false, false),
 		chan_regs + HOST1X_CHANNEL_DMACTRL);
 
 	/* set base, put, end pointer (all of memory) */
@@ -404,11 +412,11 @@ static void t20_cdma_start(struct nvhost_cdma *cdma)
 	writel(0xFFFFFFFF, chan_regs + HOST1X_CHANNEL_DMAEND);
 
 	/* reset GET */
-	writel(nvhost_channel_dmactrl(true, true, true),
+	writel(host1x_channel_dmactrl(true, true, true),
 		chan_regs + HOST1X_CHANNEL_DMACTRL);
 
 	/* start the command DMA */
-	writel(nvhost_channel_dmactrl(false, false, false),
+	writel(host1x_channel_dmactrl(false, false, false),
 		chan_regs + HOST1X_CHANNEL_DMACTRL);
 
 	cdma->running = true;
@@ -430,7 +438,7 @@ static void t20_cdma_timeout_restart(struct nvhost_cdma *cdma, u32 getptr)
 	BUG_ON(!cdma_pb_op(cdma).putptr);
 	cdma->last_put = cdma_pb_op(cdma).putptr(&cdma->push_buffer);
 
-	writel(nvhost_channel_dmactrl(true, false, false),
+	writel(host1x_channel_dmactrl(true, false, false),
 		chan_regs + HOST1X_CHANNEL_DMACTRL);
 
 	/* set base, end pointer (all of memory) */
@@ -439,7 +447,7 @@ static void t20_cdma_timeout_restart(struct nvhost_cdma *cdma, u32 getptr)
 
 	/* set GET, by loading the value in PUT (then reset GET) */
 	writel(getptr, chan_regs + HOST1X_CHANNEL_DMAPUT);
-	writel(nvhost_channel_dmactrl(true, true, true),
+	writel(host1x_channel_dmactrl(true, true, true),
 		chan_regs + HOST1X_CHANNEL_DMACTRL);
 
 	dev_dbg(&dev->pdev->dev,
@@ -450,12 +458,12 @@ static void t20_cdma_timeout_restart(struct nvhost_cdma *cdma, u32 getptr)
 		cdma->last_put);
 
 	/* deassert GET reset and set PUT */
-	writel(nvhost_channel_dmactrl(true, false, false),
+	writel(host1x_channel_dmactrl(true, false, false),
 		chan_regs + HOST1X_CHANNEL_DMACTRL);
 	writel(cdma->last_put, chan_regs + HOST1X_CHANNEL_DMAPUT);
 
 	/* start the command DMA */
-	writel(nvhost_channel_dmactrl(false, false, false),
+	writel(host1x_channel_dmactrl(false, false, false),
 		chan_regs + HOST1X_CHANNEL_DMACTRL);
 
 	cdma->running = true;
@@ -486,7 +494,7 @@ static void t20_cdma_stop(struct nvhost_cdma *cdma)
 	mutex_lock(&cdma->lock);
 	if (cdma->running) {
 		nvhost_cdma_wait_locked(cdma, CDMA_EVENT_SYNC_QUEUE_EMPTY);
-		writel(nvhost_channel_dmactrl(true, false, false),
+		writel(host1x_channel_dmactrl(true, false, false),
 			chan_regs + HOST1X_CHANNEL_DMACTRL);
 		cdma->running = false;
 	}
@@ -523,7 +531,7 @@ void t20_cdma_timeout_teardown_begin(struct nvhost_cdma *cdma)
 		"begin channel teardown (channel id %d)\n", ch->chid);
 
 	cmdproc_stop = readl(dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
-	cmdproc_stop = nvhost_sync_cmdproc_stop_chid(cmdproc_stop, ch->chid);
+	cmdproc_stop |= BIT(ch->chid);
 	writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
 
 	dev_dbg(&dev->pdev->dev,
@@ -533,7 +541,7 @@ void t20_cdma_timeout_teardown_begin(struct nvhost_cdma *cdma)
 		readl(ch->aperture + HOST1X_CHANNEL_DMAPUT),
 		cdma->last_put);
 
-	writel(nvhost_channel_dmactrl(true, false, false),
+	writel(host1x_channel_dmactrl(true, false, false),
 		ch->aperture + HOST1X_CHANNEL_DMACTRL);
 
 	writel(BIT(ch->chid), dev->sync_aperture + HOST1X_SYNC_CH_TEARDOWN);
@@ -556,7 +564,7 @@ void t20_cdma_timeout_teardown_end(struct nvhost_cdma *cdma, u32 getptr)
 		ch->chid, getptr);
 
 	cmdproc_stop = readl(dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
-	cmdproc_stop = nvhost_sync_cmdproc_run_chid(cmdproc_stop, ch->chid);
+	cmdproc_stop &= ~(BIT(ch->chid));
 	writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
 
 	cdma->torndown = false;
@@ -596,7 +604,7 @@ static void t20_cdma_timeout_handler(struct work_struct *work)
 
 	/* stop processing to get a clean snapshot */
 	prev_cmdproc = readl(dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
-	cmdproc_stop = nvhost_sync_cmdproc_stop_chid(prev_cmdproc, ch->chid);
+	cmdproc_stop = prev_cmdproc | BIT(ch->chid);
 	writel(cmdproc_stop, dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
 
 	dev_dbg(&dev->pdev->dev, "cdma_timeout: cmdproc was 0x%x is 0x%x\n",
@@ -610,8 +618,7 @@ static void t20_cdma_timeout_handler(struct work_struct *work)
 		dev_dbg(&dev->pdev->dev,
 			 "cdma_timeout: expired, but buffer had completed\n");
 		/* restore */
-		cmdproc_stop = nvhost_sync_cmdproc_run_chid(prev_cmdproc,
-			ch->chid);
+		cmdproc_stop = prev_cmdproc & ~(BIT(ch->chid));
 		writel(cmdproc_stop,
 			dev->sync_aperture + HOST1X_SYNC_CMDPROC_STOP);
 		mutex_unlock(&cdma->lock);
diff --git a/drivers/video/tegra/host/t20/cdma_t20.h b/drivers/video/tegra/host/t20/cdma_t20.h
new file mode 100644
index 000000000000..26b065548f34
--- /dev/null
+++ b/drivers/video/tegra/host/t20/cdma_t20.h
@@ -0,0 +1,41 @@
+/*
+ * drivers/video/tegra/host/t20/cdma_t20.h
+ *
+ * Tegra Graphics Host Channel
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __NVHOST_CDMA_T20_H
+#define __NVHOST_CDMA_T20_H
+
+/* Size of the sync queue. If it is too small, we won't be able to queue up
+ * many command buffers. If it is too large, we waste memory. */
+#define NVHOST_SYNC_QUEUE_SIZE 512
+
+/* Number of gathers we allow to be queued up per channel. Must be a
+ * power of two. Currently sized such that pushbuffer is 4KB (512*8B). */
+#define NVHOST_GATHER_QUEUE_SIZE 512
+
+/* 8 bytes per slot. (This number does not include the final RESTART.) */
+#define PUSH_BUFFER_SIZE (NVHOST_GATHER_QUEUE_SIZE * 8)
+
+/* 4K page containing GATHERed methods to increment channel syncpts
+ * and replaces the original timed out contexts GATHER slots */
+#define SYNCPT_INCR_BUFFER_SIZE_WORDS   (4096 / sizeof(u32))
+
+#endif
diff --git a/drivers/video/tegra/host/t20/channel_t20.c b/drivers/video/tegra/host/t20/channel_t20.c
index 6f5b1f51f11a..ec0b7c2e6cc5 100644
--- a/drivers/video/tegra/host/t20/channel_t20.c
+++ b/drivers/video/tegra/host/t20/channel_t20.c
@@ -27,15 +27,15 @@
 #include <mach/powergate.h>
 #include <linux/slab.h>
 
-#include "hardware_t20.h"
+#include "channel_t20.h"
 #include "syncpt_t20.h"
-#include "../dev.h"
 #include "3dctx_t20.h"
+
 #include "../3dctx_common.h"
 #include "mpectx_t20.h"
+#include "../nvhost_intr.h"
 
 #define NVHOST_NUMCHANNELS (NV_HOST1X_CHANNELS - 1)
-#define NVHOST_CHANNEL_BASE 0
 
 #define NVMODMUTEX_2D_FULL   (1)
 #define NVMODMUTEX_2D_SIMPLE (2)
@@ -143,7 +143,6 @@ const struct nvhost_channeldesc nvhost_t20_channelmap[] = {
 
 static inline void __iomem *t20_channel_aperture(void __iomem *p, int ndx)
 {
-	ndx += NVHOST_CHANNEL_BASE;
 	p += NV_HOST1X_CHANNEL0_BASE;
 	p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
 	return p;
@@ -488,8 +487,7 @@ static int t20_channel_read_3d_reg(
 	/* Switch to 3D - wait for it to complete what it was doing */
 	nvhost_cdma_push(&channel->cdma,
 		nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
-		nvhost_opcode_imm(NV_CLASS_HOST_INCR_SYNCPT,
-				NV_SYNCPT_OP_DONE << 8 | NVSYNCPT_3D));
+		nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE, NVSYNCPT_3D));
 	nvhost_cdma_push(&channel->cdma,
 		nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
 			NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1),
@@ -505,7 +503,8 @@ static int t20_channel_read_3d_reg(
 		NVHOST_OPCODE_NOOP);
 	/*  Increment syncpt to indicate that FIFO can be read */
 	nvhost_cdma_push(&channel->cdma,
-		nvhost_opcode_imm(NV_CLASS_HOST_INCR_SYNCPT, NVSYNCPT_3D),
+		nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE,
+			NVSYNCPT_3D),
 		NVHOST_OPCODE_NOOP);
 	/*  Wait for value to be read from FIFO */
 	nvhost_cdma_push(&channel->cdma,
@@ -518,7 +517,8 @@ static int t20_channel_read_3d_reg(
 		nvhost_class_host_incr_syncpt_base(NVWAITBASE_3D, 4));
 	nvhost_cdma_push(&channel->cdma,
 		NVHOST_OPCODE_NOOP,
-		nvhost_opcode_imm(NV_CLASS_HOST_INCR_SYNCPT, NVSYNCPT_3D));
+		nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_IMMEDIATE,
+			NVSYNCPT_3D));
 
 	/* end CDMA submit  */
 	nvhost_cdma_end(&channel->cdma, job);
@@ -578,9 +578,6 @@ done:
 
 int nvhost_init_t20_channel_support(struct nvhost_master *host)
 {
-
-	BUILD_BUG_ON(NVHOST_NUMCHANNELS != ARRAY_SIZE(nvhost_t20_channelmap));
-
 	host->nb_mlocks =  NV_HOST1X_SYNC_MLOCK_NUM;
 	host->nb_channels =  NVHOST_NUMCHANNELS;
 
@@ -601,7 +598,7 @@ int nvhost_drain_read_fifo(void __iomem *chan_regs,
 
 		while (!entries && time_before(jiffies, timeout)) {
 			/* query host for number of entries in fifo */
-			entries = nvhost_channel_fifostat_outfentries(
+			entries = HOST1X_VAL(CHANNEL_FIFOSTAT, OUTFENTRIES,
 				readl(chan_regs + HOST1X_CHANNEL_FIFOSTAT));
 			if (!entries)
 				cpu_relax();
diff --git a/drivers/video/tegra/host/t20/channel_t20.h b/drivers/video/tegra/host/t20/channel_t20.h
index dfd5be29a3e7..13ccfd004b57 100644
--- a/drivers/video/tegra/host/t20/channel_t20.h
+++ b/drivers/video/tegra/host/t20/channel_t20.h
@@ -23,8 +23,13 @@
 #ifndef __NVHOST_CHANNEL_T20_H
 #define __NVHOST_CHANNEL_T20_H
 
+#include "hardware_t20.h"
 #include "../nvhost_channel.h"
 
 extern const struct nvhost_channeldesc nvhost_t20_channelmap[];
 
+/* Reads words from FIFO */
+int nvhost_drain_read_fifo(void __iomem *chan_regs,
+		u32 *ptr, unsigned int count, unsigned int *pending);
+
 #endif
diff --git a/drivers/video/tegra/host/t20/debug_t20.c b/drivers/video/tegra/host/t20/debug_t20.c
index 2a127ef435dd..9ce8efc95570 100644
--- a/drivers/video/tegra/host/t20/debug_t20.c
+++ b/drivers/video/tegra/host/t20/debug_t20.c
@@ -29,6 +29,7 @@
 #include "../../nvmap/nvmap.h"
 
 #include "hardware_t20.h"
+#include "cdma_t20.h"
 
 #define NVHOST_DEBUG_MAX_PAGE_OFFSET 102400
 
@@ -264,14 +265,15 @@ static void t20_debug_show_channel_cdma(struct nvhost_master *m,
 	dmaput = readl(channel->aperture + HOST1X_CHANNEL_DMAPUT);
 	dmaget = readl(channel->aperture + HOST1X_CHANNEL_DMAGET);
 	dmactrl = readl(channel->aperture + HOST1X_CHANNEL_DMACTRL);
-	cbread = readl(m->aperture + HOST1X_SYNC_CBREAD(chid));
-	cbstat = readl(m->aperture + HOST1X_SYNC_CBSTAT(chid));
+	cbread = readl(m->sync_aperture + HOST1X_SYNC_CBREAD_x(chid));
+	cbstat = readl(m->sync_aperture + HOST1X_SYNC_CBSTAT_x(chid));
 
 	nvhost_debug_output(o, "%d-%s (%d): ", chid,
 			    channel->mod.name,
 			    channel->mod.refcount);
 
-	if ((dmactrl & 1) || !channel->cdma.push_buffer.mapped) {
+	if (HOST1X_VAL(CHANNEL_DMACTRL, DMASTOP, dmactrl)
+		|| !channel->cdma.push_buffer.mapped) {
 		nvhost_debug_output(o, "inactive\n\n");
 		return;
 	}
@@ -284,8 +286,9 @@ static void t20_debug_show_channel_cdma(struct nvhost_master *m,
 
 	case 0x00010009:
 		base = (cbread >> 16) & 0xff;
-		val = readl(m->aperture + HOST1X_SYNC_SYNCPT_BASE(base));
-		baseval = val & 0xffff;
+		val = readl(m->sync_aperture +
+				HOST1X_SYNC_SYNCPT_BASE_x(base));
+		baseval = HOST1X_VAL(SYNC_SYNCPT_BASE_0, BASE, val);
 		val = cbread & 0xffff;
 		nvhost_debug_output(o, "waiting on syncpt %d val %d "
 			  "(base %d = %d; offset = %d)\n",
@@ -296,7 +299,9 @@ static void t20_debug_show_channel_cdma(struct nvhost_master *m,
 	default:
 		nvhost_debug_output(o,
 				"active class %02x, offset %04x, val %08x\n",
-			cbstat >> 16, cbstat & 0xffff, cbread);
+				HOST1X_VAL(SYNC_CBSTAT_0, CBCLASS0, cbstat),
+				HOST1X_VAL(SYNC_CBSTAT_0, CBOFFSET0, cbstat),
+				cbread);
 		break;
 	}
 
@@ -320,30 +325,33 @@ void t20_debug_show_channel_fifo(struct nvhost_master *m,
 
 	val = readl(channel->aperture + HOST1X_CHANNEL_FIFOSTAT);
 	nvhost_debug_output(o, "FIFOSTAT %08x\n", val);
-	if (val & (1 << 10)) {
+	if (HOST1X_VAL(CHANNEL_FIFOSTAT, CFEMPTY, val)) {
 		nvhost_debug_output(o, "[empty]\n");
 		return;
 	}
 
-	writel(0x0, m->aperture + HOST1X_SYNC_CFPEEK_CTRL);
-	writel((1 << 31) | (chid << 16),
-		m->aperture + HOST1X_SYNC_CFPEEK_CTRL);
+	writel(0x0, m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+	writel(HOST1X_CREATE(SYNC_CFPEEK_CTRL, ENA, 1)
+			| HOST1X_CREATE(SYNC_CFPEEK_CTRL, CHANNR, chid),
+		m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
 
-	val = readl(m->aperture + HOST1X_SYNC_CFPEEK_PTRS);
-	rd_ptr = val & 0x1ff;
-	wr_ptr = (val >> 16) & 0x1ff;
+	val = readl(m->sync_aperture + HOST1X_SYNC_CFPEEK_PTRS);
+	rd_ptr = HOST1X_VAL(SYNC_CFPEEK_PTRS, CF_RD_PTR, val);
+	wr_ptr = HOST1X_VAL(SYNC_CFPEEK_PTRS, CF_WR_PTR, val);
 
-	val = readl(m->aperture + HOST1X_SYNC_CF_SETUP(chid));
-	start = val & 0x1ff;
-	end = (val >> 16) & 0x1ff;
+	val = readl(m->sync_aperture + HOST1X_SYNC_CFx_SETUP(chid));
+	start = HOST1X_VAL(SYNC_CF0_SETUP, BASE, val);
+	end = HOST1X_VAL(SYNC_CF0_SETUP, LIMIT, val);
 
 	state = NVHOST_DBG_STATE_CMD;
 
 	do {
-		writel(0x0, m->aperture + HOST1X_SYNC_CFPEEK_CTRL);
-		writel((1 << 31) | (chid << 16) | rd_ptr,
-			m->aperture + HOST1X_SYNC_CFPEEK_CTRL);
-		val = readl(m->aperture + HOST1X_SYNC_CFPEEK_READ);
+		writel(0x0, m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+		writel(HOST1X_CREATE(SYNC_CFPEEK_CTRL, ENA, 1)
+				| HOST1X_CREATE(SYNC_CFPEEK_CTRL, CHANNR, chid)
+				| HOST1X_CREATE(SYNC_CFPEEK_CTRL, ADDR, rd_ptr),
+			m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
+		val = readl(m->sync_aperture + HOST1X_SYNC_CFPEEK_READ);
 
 		show_channel_word(o, &state, &count, 0, val, NULL);
 
@@ -357,7 +365,7 @@ void t20_debug_show_channel_fifo(struct nvhost_master *m,
 		nvhost_debug_output(o, ", ...])\n");
 	nvhost_debug_output(o, "\n");
 
-	writel(0x0, m->aperture + HOST1X_SYNC_CFPEEK_CTRL);
+	writel(0x0, m->sync_aperture + HOST1X_SYNC_CFPEEK_CTRL);
 }
 
 static void t20_debug_show_mlocks(struct nvhost_master *m, struct output *o)
@@ -368,10 +376,10 @@ static void t20_debug_show_mlocks(struct nvhost_master *m, struct output *o)
 	nvhost_debug_output(o, "---- mlocks ----\n");
 	for (i = 0; i < NV_HOST1X_NB_MLOCKS; i++) {
 		u32 owner = readl(mlo_regs + i);
-		if (owner & 0x1)
+		if (HOST1X_VAL(SYNC_MLOCK_OWNER_0, CH_OWNS, owner))
 			nvhost_debug_output(o, "%d: locked by channel %d\n",
-				i, (owner >> 8) & 0xf);
-		else if (owner & 0x2)
+				i, HOST1X_VAL(SYNC_MLOCK_OWNER_0, CHID, owner));
+		else if (HOST1X_VAL(SYNC_MLOCK_OWNER_0, CPU_OWNS, owner))
 			nvhost_debug_output(o, "%d: locked by cpu\n", i);
 		else
 			nvhost_debug_output(o, "%d: unlocked\n", i);
diff --git a/drivers/video/tegra/host/t20/hardware_t20.h b/drivers/video/tegra/host/t20/hardware_t20.h
index 4cc83f79ec81..c36d3a94932f 100644
--- a/drivers/video/tegra/host/t20/hardware_t20.h
+++ b/drivers/video/tegra/host/t20/hardware_t20.h
@@ -40,111 +40,105 @@ enum {
 #define NV_HOST1X_CHANNEL_MAP_SIZE_BYTES 16384
 #define NV_HOST1X_SYNC_MLOCK_NUM 16
 
+#define HOST1X_VAL(reg, field, regdata) \
+	((regdata >> HOST1X_##reg##_##field##_SHIFT) \
+			& HOST1X_##reg##_##field##_MASK)
+#define HOST1X_CREATE(reg, field, data) \
+	((data & HOST1X_##reg##_##field##_MASK) \
+			<< HOST1X_##reg##_##field##_SHIFT) \
+
 #define HOST1X_CHANNEL_FIFOSTAT		0x00
+#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_SHIFT 10
+#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_MASK 0x1
+#define HOST1X_CHANNEL_FIFOSTAT_OUTFENTRIES_SHIFT 24
+#define HOST1X_CHANNEL_FIFOSTAT_OUTFENTRIES_MASK 0x1f
 #define HOST1X_CHANNEL_INDDATA		0x0c
 #define HOST1X_CHANNEL_DMASTART		0x14
 #define HOST1X_CHANNEL_DMAPUT		0x18
 #define HOST1X_CHANNEL_DMAGET		0x1c
 #define HOST1X_CHANNEL_DMAEND		0x20
 #define HOST1X_CHANNEL_DMACTRL		0x24
-
-#define HOST1X_SYNC_CF_SETUP(x)		(0x3080 + (4 * (x)))
-
-#define HOST1X_SYNC_SYNCPT_BASE(x)	(0x3600 + (4 * (x)))
-
-#define HOST1X_SYNC_CBREAD(x)		(0x3720 + (4 * (x)))
-#define HOST1X_SYNC_CFPEEK_CTRL		0x374c
-#define HOST1X_SYNC_CFPEEK_READ		0x3750
-#define HOST1X_SYNC_CFPEEK_PTRS		0x3754
-#define HOST1X_SYNC_CBSTAT(x)		(0x3758 + (4 * (x)))
-
-static inline unsigned nvhost_channel_fifostat_outfentries(u32 reg)
-{
-	return (reg >> 24) & 0x1f;
-}
-
-static inline u32 nvhost_channel_dmactrl(bool stop, bool get_rst, bool init_get)
-{
-	u32 v = stop ? 1 : 0;
-	if (get_rst)
-		v |= 2;
-	if (init_get)
-		v |= 4;
-	return v;
-}
-
+#define HOST1X_CHANNEL_DMACTRL_DMASTOP_SHIFT 0
+#define HOST1X_CHANNEL_DMACTRL_DMASTOP_MASK 0x1
+#define HOST1X_CHANNEL_DMACTRL_DMAGETRST_SHIFT 1
+#define HOST1X_CHANNEL_DMACTRL_DMAGETRST_MASK 0x1
+#define HOST1X_CHANNEL_DMACTRL_DMAINITGET_SHIFT 2
+#define HOST1X_CHANNEL_DMACTRL_DMAINITGET_MASK 0x1
+
+#define HOST1X_CHANNEL_SYNC_REG_BASE	0x3000
+
+#define HOST1X_SYNC_INTMASK		0x4
+#define HOST1X_SYNC_INTC0MASK		0x8
+#define HOST1X_SYNC_HINTSTATUS		0x20
+#define HOST1X_SYNC_HINTMASK		0x24
+#define HOST1X_SYNC_HINTSTATUS_EXT	0x28
+#define HOST1X_SYNC_HINTSTATUS_EXT_IP_READ_INT_SHIFT 30
+#define HOST1X_SYNC_HINTSTATUS_EXT_IP_READ_INT_MASK 0x1
+#define HOST1X_SYNC_HINTSTATUS_EXT_IP_WRITE_INT_SHIFT 31
+#define HOST1X_SYNC_HINTSTATUS_EXT_IP_WRITE_INT_MASK 0x1
+#define HOST1X_SYNC_HINTMASK_EXT	0x2c
+#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS 0x40
+#define HOST1X_SYNC_SYNCPT_THRESH_CPU1_INT_STATUS 0x48
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE 0x60
+#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0 0x68
+#define HOST1X_SYNC_CF0_SETUP		0x80
+#define HOST1X_SYNC_CF0_SETUP_BASE_SHIFT 0
+#define HOST1X_SYNC_CF0_SETUP_BASE_MASK	0x1ff
+#define HOST1X_SYNC_CF0_SETUP_LIMIT_SHIFT 16
+#define HOST1X_SYNC_CF0_SETUP_LIMIT_MASK 0x1ff
+#define HOST1X_SYNC_CFx_SETUP(x)	(HOST1X_SYNC_CF0_SETUP + (4 * (x)))
+
+#define HOST1X_SYNC_CMDPROC_STOP	0xac
+#define HOST1X_SYNC_CH_TEARDOWN		0xb0
+#define HOST1X_SYNC_USEC_CLK		0x1a4
+#define HOST1X_SYNC_CTXSW_TIMEOUT_CFG	0x1a8
+#define HOST1X_SYNC_IP_BUSY_TIMEOUT	0x1bc
+#define HOST1X_SYNC_IP_READ_TIMEOUT_ADDR 0x1c0
+#define HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR 0x1c4
+#define HOST1X_SYNC_MLOCK_0		0x2c0
+#define HOST1X_SYNC_MLOCK_OWNER_0	0x340
+#define HOST1X_SYNC_MLOCK_OWNER_0_CHID_SHIFT 8
+#define HOST1X_SYNC_MLOCK_OWNER_0_CHID_MASK 0xf
+#define HOST1X_SYNC_MLOCK_OWNER_0_CPU_OWNS_SHIFT 1
+#define HOST1X_SYNC_MLOCK_OWNER_0_CPU_OWNS_MASK 0x1
+#define HOST1X_SYNC_MLOCK_OWNER_0_CH_OWNS_SHIFT 0
+#define HOST1X_SYNC_MLOCK_OWNER_0_CH_OWNS_MASK 0x1
+#define HOST1X_SYNC_SYNCPT_0		0x400
+#define HOST1X_SYNC_SYNCPT_INT_THRESH_0	0x500
+
+#define HOST1X_SYNC_SYNCPT_BASE_0	0x600
+#define HOST1X_SYNC_SYNCPT_BASE_0_BASE_SHIFT 0
+#define HOST1X_SYNC_SYNCPT_BASE_0_BASE_MASK 0xffff
+#define HOST1X_SYNC_SYNCPT_BASE_x(x)	(HOST1X_SYNC_SYNCPT_BASE_0 + (4 * (x)))
+
+#define HOST1X_SYNC_SYNCPT_CPU_INCR	0x700
+
+#define HOST1X_SYNC_CBREAD_0		0x720
+#define HOST1X_SYNC_CBREAD_x(x)		(HOST1X_SYNC_CBREAD_0 + (4 * (x)))
+#define HOST1X_SYNC_CFPEEK_CTRL		0x74c
+#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_SHIFT 0
+#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_MASK 0x1ff
+#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_SHIFT 16
+#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_MASK 0x7
+#define HOST1X_SYNC_CFPEEK_CTRL_ENA_SHIFT 31
+#define HOST1X_SYNC_CFPEEK_CTRL_ENA_MASK 0x1
+#define HOST1X_SYNC_CFPEEK_READ		0x750
+#define HOST1X_SYNC_CFPEEK_PTRS		0x754
+#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_SHIFT 0
+#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_MASK 0x1ff
+#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_SHIFT 16
+#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_MASK 0x1ff
+#define HOST1X_SYNC_CBSTAT_0		0x758
+#define HOST1X_SYNC_CBSTAT_0_CBOFFSET0_SHIFT 0
+#define HOST1X_SYNC_CBSTAT_0_CBOFFSET0_MASK 0xffff
+#define HOST1X_SYNC_CBSTAT_0_CBCLASS0_SHIFT 16
+#define HOST1X_SYNC_CBSTAT_0_CBCLASS0_MASK 0xffff
+#define HOST1X_SYNC_CBSTAT_x(x)		(HOST1X_SYNC_CBSTAT_0 + (4 * (x)))
 
 /* sync registers */
 #define NV_HOST1X_SYNCPT_NB_PTS 32
 #define NV_HOST1X_SYNCPT_NB_BASES 8
 #define NV_HOST1X_NB_MLOCKS 16
-#define HOST1X_CHANNEL_SYNC_REG_BASE 12288
-
-enum {
-	HOST1X_SYNC_INTMASK = 0x4,
-	HOST1X_SYNC_INTC0MASK = 0x8,
-	HOST1X_SYNC_HINTSTATUS = 0x20,
-	HOST1X_SYNC_HINTMASK = 0x24,
-	HOST1X_SYNC_HINTSTATUS_EXT = 0x28,
-	HOST1X_SYNC_HINTMASK_EXT = 0x2c,
-	HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS = 0x40,
-	HOST1X_SYNC_SYNCPT_THRESH_CPU1_INT_STATUS = 0x48,
-	HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE = 0x60,
-	HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0 = 0x68,
-	HOST1X_SYNC_CMDPROC_STOP = 0xac,
-	HOST1X_SYNC_CH_TEARDOWN = 0xb0,
-	HOST1X_SYNC_USEC_CLK = 0x1a4,
-	HOST1X_SYNC_CTXSW_TIMEOUT_CFG = 0x1a8,
-	HOST1X_SYNC_IP_BUSY_TIMEOUT = 0x1bc,
-	HOST1X_SYNC_IP_READ_TIMEOUT_ADDR = 0x1c0,
-	HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR = 0x1c4,
-	HOST1X_SYNC_MLOCK_0 = 0x2c0,
-	HOST1X_SYNC_MLOCK_OWNER_0 = 0x340,
-	HOST1X_SYNC_SYNCPT_0 = 0x400,
-	HOST1X_SYNC_SYNCPT_INT_THRESH_0 = 0x500,
-	HOST1X_SYNC_SYNCPT_BASE_0 = 0x600,
-	HOST1X_SYNC_SYNCPT_CPU_INCR = 0x700
-};
-
-static inline bool nvhost_sync_hintstatus_ext_ip_read_int(u32 reg)
-{
-	return (reg & BIT(30)) != 0;
-}
-
-static inline bool nvhost_sync_hintstatus_ext_ip_write_int(u32 reg)
-{
-	return (reg & BIT(31)) != 0;
-}
-
-static inline bool nvhost_sync_mlock_owner_ch_owns(u32 reg)
-{
-	return (reg & BIT(0)) != 0;
-}
-
-static inline bool nvhost_sync_mlock_owner_cpu_owns(u32 reg)
-{
-	return (reg & BIT(1)) != 0;
-}
-
-static inline unsigned int nvhost_sync_mlock_owner_owner_chid(u32 reg)
-{
-	return (reg >> 8) & 0xf;
-}
-
-static inline unsigned int nvhost_sync_cmdproc_stop_chid(u32 reg, u32 chid)
-{
-	return reg | BIT(chid);
-}
-
-static inline unsigned int nvhost_sync_cmdproc_run_chid(u32 reg, u32 chid)
-{
-	return reg & ~(BIT(chid));
-}
-
-static inline unsigned int nvhost_sync_ch_teardown_chid(u32 reg, u32 chid)
-{
-	return reg | BIT(chid);
-}
 
 /* host class methods */
 enum {
@@ -279,25 +273,4 @@ static inline u32 nvhost_mask2(unsigned x, unsigned y)
 	return 1 | (1 << (y - x));
 }
 
-/* Reads words from FIFO */
-int nvhost_drain_read_fifo(void __iomem *chan_regs,
-		u32 *ptr, unsigned int count, unsigned int *pending);
-
-/*
- * Size of the sync queue. Size equals to case where all submits consist of
- * only one gather.
- */
-#define NVHOST_SYNC_QUEUE_SIZE 512
-
-/* Number of gathers we allow to be queued up per channel. Must be a
- * power of two. Currently sized such that pushbuffer is 4KB (512*8B). */
-#define NVHOST_GATHER_QUEUE_SIZE 512
-
-/* 8 bytes per slot. (This number does not include the final RESTART.) */
-#define PUSH_BUFFER_SIZE (NVHOST_GATHER_QUEUE_SIZE * 8)
-
-/* 4K page containing GATHERed methods to increment channel syncpts
- * and replaces the original timed out contexts GATHER slots */
-#define SYNCPT_INCR_BUFFER_SIZE_WORDS   (4096 / sizeof(u32))
-
 #endif /* __NVHOST_HARDWARE_T20_H */
diff --git a/drivers/video/tegra/host/t20/intr_t20.c b/drivers/video/tegra/host/t20/intr_t20.c
index 7df3c1e959e9..499246d6fd81 100644
--- a/drivers/video/tegra/host/t20/intr_t20.c
+++ b/drivers/video/tegra/host/t20/intr_t20.c
@@ -77,9 +77,9 @@ static void t20_intr_disable_all_syncpt_intrs(struct nvhost_intr *intr)
 	writel(0, sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE);
 
 	/* clear status for both cpu's */
-	writel(0xfffffffful, sync_regs +
+	writel(0xffffffffu, sync_regs +
 		HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);
-	writel(0xfffffffful, sync_regs +
+	writel(0xffffffffu, sync_regs +
 		HOST1X_SYNC_SYNCPT_THRESH_CPU1_INT_STATUS);
 }
 
@@ -118,12 +118,12 @@ static irqreturn_t t20_intr_host1x_isr(int irq, void *dev_id)
 	stat = readl(sync_regs + HOST1X_SYNC_HINTSTATUS);
 	ext_stat = readl(sync_regs + HOST1X_SYNC_HINTSTATUS_EXT);
 
-	if (nvhost_sync_hintstatus_ext_ip_read_int(ext_stat)) {
+	if (HOST1X_VAL(SYNC_HINTSTATUS_EXT, IP_READ_INT, ext_stat)) {
 		addr = readl(sync_regs + HOST1X_SYNC_IP_READ_TIMEOUT_ADDR);
 		pr_err("Host read timeout at address %x\n", addr);
 	}
 
-	if (nvhost_sync_hintstatus_ext_ip_write_int(ext_stat)) {
+	if (HOST1X_VAL(SYNC_HINTSTATUS_EXT, IP_WRITE_INT, ext_stat)) {
 		addr = readl(sync_regs + HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR);
 		pr_err("Host write timeout at address %x\n", addr);
 	}
diff --git a/drivers/video/tegra/host/t20/mpectx_t20.c b/drivers/video/tegra/host/t20/mpectx_t20.c
index 21dc579211c0..d94c804528ed 100644
--- a/drivers/video/tegra/host/t20/mpectx_t20.c
+++ b/drivers/video/tegra/host/t20/mpectx_t20.c
@@ -23,6 +23,7 @@
 #include "../nvhost_hwctx.h"
 #include "../dev.h"
 #include "hardware_t20.h"
+#include "channel_t20.h"
 #include "syncpt_t20.h"
 #include "t20.h"
 #include <linux/slab.h>
diff --git a/drivers/video/tegra/host/t30/3dctx_t30.c b/drivers/video/tegra/host/t30/3dctx_t30.c
index 5f5efd599a1f..2eb7eda76dc6 100644
--- a/drivers/video/tegra/host/t30/3dctx_t30.c
+++ b/drivers/video/tegra/host/t30/3dctx_t30.c
@@ -25,6 +25,7 @@
 #include "../t20/hardware_t20.h"
 #include "../t20/syncpt_t20.h"
 #include "../3dctx_common.h"
+#include "../3d_common.h"
 
 #include <mach/gpufuse.h>
 #include <mach/hardware.h>
@@ -131,18 +132,19 @@ static void save_push_v1(struct nvhost_cdma *cdma,
 	   and send their reads to memory */
 	if (register_sets == 2) {
 		nvhost_cdma_push(cdma,
-				nvhost_opcode_imm(0xb00, 2),
-				nvhost_opcode_imm(0xe40, 1));
+			nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK, 2),
+			nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS,
+					1));
 		nvhost_cdma_push(cdma,
 				nvhost_opcode_nonincr(0x904, 1),
 				ctx->restore_phys + restore_set1_offset * 4);
 	}
 	nvhost_cdma_push(cdma,
-			nvhost_opcode_imm(0xb00, 1),
-			nvhost_opcode_imm(0xe40, 1));
+		nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK, 1),
+		nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 1));
 	nvhost_cdma_push(cdma,
-			nvhost_opcode_nonincr(0x904, 1),
-			ctx->restore_phys);
+		nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_ADDRESS, 1),
+		ctx->restore_phys);
 	/* gather the save buffer */
 	nvhost_cdma_push_gather(cdma,
 			(void *)NVHOST_CDMA_PUSH_GATHER_CTXSAVE,
@@ -153,17 +155,16 @@ static void save_push_v1(struct nvhost_cdma *cdma,
 
 static void __init save_begin_v1(u32 *ptr)
 {
-	ptr[0] = nvhost_opcode_nonincr(0x905, RESTORE_BEGIN_SIZE);
+	ptr[0] = nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_DATA,
+			RESTORE_BEGIN_SIZE);
 	nvhost_3dctx_restore_begin(ptr + 1);
 	ptr += RESTORE_BEGIN_SIZE;
 }
 
 static void __init save_direct_v1(u32 *ptr, u32 start_reg, u32 count)
 {
-#if RESTORE_DIRECT_SIZE != 1
-#error whoops! code is optimized for RESTORE_DIRECT_SIZE == 1
-#endif
-	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0x905, 1);
+	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID,
+			AR3D_DW_MEMORY_OUTPUT_DATA, 1);
 	nvhost_3dctx_restore_direct(ptr + 1, start_reg, count);
 	ptr += RESTORE_DIRECT_SIZE;
 	ptr[1] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
@@ -178,7 +179,8 @@ static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
 			u32 data_reg, u32 count)
 {
 	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
-	ptr[1] = nvhost_opcode_nonincr(0x905, RESTORE_INDIRECT_SIZE);
+	ptr[1] = nvhost_opcode_nonincr(AR3D_DW_MEMORY_OUTPUT_DATA,
+			RESTORE_INDIRECT_SIZE);
 	nvhost_3dctx_restore_indirect(ptr + 2, offset_reg, offset, data_reg,
 			count);
 	ptr += RESTORE_INDIRECT_SIZE;
@@ -192,14 +194,14 @@ static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
 
 static void __init save_end_v1(u32 *ptr)
 {
-#if RESTORE_END_SIZE != 1
-#error whoops! code is optimized for RESTORE_END_SIZE == 1
-#endif
 	/* write end of restore buffer */
-	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0x905, 1);
+	ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID,
+			AR3D_DW_MEMORY_OUTPUT_DATA, 1);
 	nvhost_3dctx_restore_end(ptr + 1);
 	ptr += RESTORE_END_SIZE;
-	ptr[1] = nvhost_opcode_imm(0xb00, (1 << register_sets) - 1);
+	/* reset to dual reg if necessary */
+	ptr[1] = nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK,
+			(1 << register_sets) - 1);
 	/* op_done syncpt incr to flush FDC */
 	ptr[2] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE, NVSYNCPT_3D);
 	/* host wait for that syncpt incr, and advance the wait base */
@@ -215,7 +217,7 @@ static void __init save_end_v1(u32 *ptr)
 	/* set class back to 3d */
 	ptr[6] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
 	/* send reg reads back to host */
-	ptr[7] = nvhost_opcode_imm(0xe40, 0);
+	ptr[7] = nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 0);
 	/* final syncpt increment to release waiters */
 	ptr[8] = nvhost_opcode_imm(0, NVSYNCPT_3D);
 }
@@ -289,12 +291,14 @@ static void __init switch_gpu(struct save_info *info,
 {
 	if (info->ptr) {
 		info->ptr[0] = nvhost_opcode_setclass(
-				NV_GRAPHICS_3D_CLASS_ID, 0x905, 1);
-		info->ptr[1] = nvhost_opcode_imm(0xb00,
+				NV_GRAPHICS_3D_CLASS_ID,
+				AR3D_DW_MEMORY_OUTPUT_DATA, 1);
+		info->ptr[1] = nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK,
 				restore_dest_sets);
-		info->ptr[2] = nvhost_opcode_imm(0xb00,
+		info->ptr[2] = nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK,
 				save_dest_sets);
-		info->ptr[3] = nvhost_opcode_imm(0xb01, save_src_set);
+		info->ptr[3] = nvhost_opcode_imm(AR3D_GSHIM_READ_SELECT,
+				save_src_set);
 		info->ptr += 4;
 	}
 	info->save_count += 4;
@@ -319,7 +323,7 @@ static void __init setup_save(u32 *ptr)
 		info.ptr += SAVE_BEGIN_V1_SIZE;
 	}
 
-	/* read from set0, write cmds through set0, restore to sets 0 and 1 */
+	/* read from set0, write cmds through set0, restore to set0 and 1 */
 	if (register_sets == 2)
 		switch_gpu(&info, 0, 1, 3);
 
@@ -328,7 +332,7 @@ static void __init setup_save(u32 *ptr)
 			ctxsave_regs_3d_global,
 			ARRAY_SIZE(ctxsave_regs_3d_global));
 
-	/* read from set 0, write cmds through set 0, restore to set 0 */
+	/* read from set 0, write cmds through set0, restore to set0 */
 	if (register_sets == 2)
 		switch_gpu(&info, 0, 1, 1);
 
@@ -348,7 +352,7 @@ static void __init setup_save(u32 *ptr)
 				ARRAY_SIZE(ctxsave_regs_3d_perset));
 	}
 
-	/* read from set 0, write cmds through set 1, restore to sets 0 and 1 */
+	/* read from set0, write cmds through set1, restore to set0 and 1 */
 	if (register_sets == 2)
 		switch_gpu(&info, 0, 2, 3);
 
@@ -362,7 +366,8 @@ static void __init setup_save(u32 *ptr)
 	save_size = info.save_count + save_end_size;
 	nvhost_3dctx_restore_size = info.restore_count + RESTORE_END_SIZE;
 	nvhost_3dctx_save_incrs = info.save_incrs;
-	nvhost_3dctx_save_thresh = nvhost_3dctx_save_incrs - SAVE_THRESH_OFFSET;
+	nvhost_3dctx_save_thresh = nvhost_3dctx_save_incrs
+			- SAVE_THRESH_OFFSET;
 	nvhost_3dctx_restore_incrs = info.restore_incrs;
 }
 
diff --git a/drivers/video/tegra/host/t30/channel_t30.c b/drivers/video/tegra/host/t30/channel_t30.c
index 0bd7e5246635..876870d77ead 100644
--- a/drivers/video/tegra/host/t30/channel_t30.c
+++ b/drivers/video/tegra/host/t30/channel_t30.c
@@ -22,9 +22,12 @@
 
 #include <linux/mutex.h>
 #include <mach/powergate.h>
+
+#include "3dctx_t30.h"
+#include "scale3d.h"
+
 #include "../dev.h"
 #include "../t20/channel_t20.h"
-#include "../t20/hardware_t20.h"
 #include "../t20/t20.h"
 #include "../t20/syncpt_t20.h"
 #include "../3dctx_common.h"
@@ -41,7 +44,6 @@
 #define NVMODMUTEX_DISPLAYB  (7)
 #define NVMODMUTEX_VI        (8)
 #define NVMODMUTEX_DSI       (9)
-#define NV_FIFO_READ_TIMEOUT 200000
 
 #ifndef TEGRA_POWERGATE_3D1
 #define TEGRA_POWERGATE_3D1 -1