diff options
author | Jason Chen <b02280@freescale.com> | 2010-11-17 17:29:12 +0800 |
---|---|---|
committer | Scott Sweeny <scott.sweeny@timesys.com> | 2011-01-19 11:50:26 -0500 |
commit | 25b4f98a475d18b8f9b2f1d0796238c5bf6e3c80 (patch) | |
tree | bf8051f301956c6928cd128db72c352a7cb920c3 /drivers | |
parent | a71540143c31a66807e22bf3c520620461570d69 (diff) |
ENGR00122167-1 ipuv3: adding VGA support.
Add VGA support for ipu basic driver and fb driver.
Signed-off-by: Jason Chen <b02280@freescale.com>
(cherry picked from commit 214d8593acc37e2d5ed32e75a6518a8e306a1246)
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mxc/ipu3/ipu_common.c | 1 | ||||
-rw-r--r-- | drivers/mxc/ipu3/ipu_disp.c | 58 | ||||
-rw-r--r-- | drivers/mxc/ipu3/ipu_regs.h | 1 | ||||
-rw-r--r-- | drivers/video/mxc/mxc_ipuv3_fb.c | 14 |
4 files changed, 73 insertions, 1 deletions
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index 73e22cdae726..620d17f439f6 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -2459,6 +2459,7 @@ ipu_color_space_t format_to_colorspace(uint32_t fmt) case IPU_PIX_FMT_RGB565: case IPU_PIX_FMT_BGR24: case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_GBR24: case IPU_PIX_FMT_BGR32: case IPU_PIX_FMT_BGRA32: case IPU_PIX_FMT_RGB32: diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c index 77f2fb92ae4f..f87ad9b6384f 100644 --- a/drivers/mxc/ipu3/ipu_disp.c +++ b/drivers/mxc/ipu3/ipu_disp.c @@ -880,6 +880,10 @@ void _ipu_init_dc_mappings(void) _ipu_dc_map_link(11, 5, 1, 5, 2, 5, 0); _ipu_dc_map_clear(12); _ipu_dc_map_link(12, 5, 2, 5, 1, 5, 0); + + /* IPU_PIX_FMT_GBR24 */ + _ipu_dc_map_clear(13); + _ipu_dc_map_link(13, 0, 2, 0, 0, 0, 1); } int _ipu_pixfmt_to_map(uint32_t fmt) @@ -904,6 +908,8 @@ int _ipu_pixfmt_to_map(uint32_t fmt) return 10; case IPU_PIX_FMT_YVYU: return 12; + case IPU_PIX_FMT_GBR24: + return 13; } return -1; @@ -962,6 +968,48 @@ void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk, } /*! + * This function is called to set delayed hsync/vsync for TVE-VGA mode. + * + */ +void ipu_set_vga_delayed_hsync_vsync(uint32_t width, uint32_t height, + uint32_t h_start_width, uint32_t h_sync_width, + uint32_t h_end_width, uint32_t v_start_width, + uint32_t v_sync_width, uint32_t v_end_width, + uint32_t hsync_delay, uint32_t vsync_delay, + uint32_t hsync_polarity, uint32_t vsync_polarity) +{ + int h_total, v_total; + uint32_t di_gen, disp = 1; + + h_total = width + h_start_width + h_sync_width + h_end_width; + v_total = height + v_start_width + v_sync_width + v_end_width; + + /* couter 7 for delay HSYNC */ + _ipu_di_sync_config(disp, 7, h_total - 1, + DI_SYNC_CLK, hsync_delay, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, + DI_SYNC_CLK, 0, h_sync_width * 2); + + /* couter 8 for delay VSYNC */ + _ipu_di_sync_config(disp, 8, v_total - 1, + DI_SYNC_INT_HSYNC, vsync_delay, DI_SYNC_INT_HSYNC, 0, + DI_SYNC_NONE, 1, DI_SYNC_NONE, + DI_SYNC_INT_HSYNC, 0, v_sync_width * 2); + + di_gen = __raw_readl(DI_GENERAL(disp)); + di_gen &= ~DI_GEN_POLARITY_2; + di_gen &= ~DI_GEN_POLARITY_3; + di_gen &= ~DI_GEN_POLARITY_7; + di_gen &= ~DI_GEN_POLARITY_8; + if (hsync_polarity) + di_gen |= DI_GEN_POLARITY_7; + if (vsync_polarity) + di_gen |= DI_GEN_POLARITY_8; + __raw_writel(di_gen, DI_GENERAL(disp)); +} +EXPORT_SYMBOL(ipu_set_vga_delayed_hsync_vsync); + +/*! * This function is called to initialize a synchronous LCD panel. * * @param disp The DI the panel is attached to. @@ -1030,6 +1078,9 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, /* Init clocking */ dev_dbg(g_ipu_dev, "pixel clk = %d\n", pixel_clk); + /*clear DI*/ + __raw_writel((1 << 21), DI_GENERAL(disp)); + if (sig.ext_clk) { /* * Set the PLL to be an even multiple of the pixel clock. @@ -1046,7 +1097,9 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, while (rounded_pixel_clk < 150000000) rounded_pixel_clk += pixel_clk * 2; clk_set_rate(di_parent, rounded_pixel_clk); - clk_set_rate(g_di_clk[disp], pixel_clk); + rounded_pixel_clk = + clk_round_rate(g_di_clk[disp], pixel_clk); + clk_set_rate(g_di_clk[disp], rounded_pixel_clk); } } clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]); @@ -1432,6 +1485,9 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, (pixel_fmt == IPU_PIX_FMT_VYUY)) di_gen |= 0x00020000; + if (!sig.clk_pol) + di_gen |= DI_GEN_POLARITY_DISP_CLK; + __raw_writel(di_gen, DI_GENERAL(disp)); if (!ipu_freq_scaling_enabled) diff --git a/drivers/mxc/ipu3/ipu_regs.h b/drivers/mxc/ipu3/ipu_regs.h index e8b067a060d8..002bb96b9f66 100644 --- a/drivers/mxc/ipu3/ipu_regs.h +++ b/drivers/mxc/ipu3/ipu_regs.h @@ -576,6 +576,7 @@ enum { DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16, DI_GEN_DI_CLK_EXT = 0x100000, + DI_GEN_POLARITY_DISP_CLK = 0x00020000, DI_GEN_POLARITY_1 = 0x00000001, DI_GEN_POLARITY_2 = 0x00000002, DI_GEN_POLARITY_3 = 0x00000004, diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c index 50c8b0110485..f288039d948d 100644 --- a/drivers/video/mxc/mxc_ipuv3_fb.c +++ b/drivers/video/mxc/mxc_ipuv3_fb.c @@ -1109,6 +1109,16 @@ static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg) return -EFAULT; break; } + case MXCFB_SET_DIFMT: + { + struct mxcfb_info *mxc_fbi = + (struct mxcfb_info *)fbi->par; + + if (get_user(mxc_fbi->ipu_di_pix_fmt, argp)) + return -EFAULT; + + break; + } default: retval = -EINVAL; } @@ -1804,6 +1814,10 @@ static int mxcfb_option_setup(struct fb_info *info, char *options) mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_BGR24; continue; } + if (!strncmp(opt, "GBR24", 5)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_GBR24; + continue; + } if (!strncmp(opt, "RGB565", 6)) { mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB565; continue; |