diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2017-09-27 13:00:39 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2017-10-02 15:16:10 +0200 |
| commit | 6fe6616d602eda1f1bb150871baad69687f43224 (patch) | |
| tree | 3d33f236ed9d4959cf3ce76a2f3b94273ae95952 /drivers | |
| parent | 3f5660b1cbb09c65319c452ca9dc26a572aacc6d (diff) | |
Revert "mtd: fsl-quadspi: fix macro collision problems with READ/WRITE"
This reverts commit 9386aae907d9ee79d54640f09d70909393e0ddeb.
The fsl-quadspi from mainline is implemented differently, so do not
use it from the mainline backport.
Required to also revert merge conflict resolution.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/spi-nor/fsl-quadspi.c | 23 |
1 files changed, 9 insertions, 14 deletions
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 50f3b085b227..f769c5add3aa 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -164,15 +164,15 @@ #define LUT_MODE 4 #define LUT_MODE2 5 #define LUT_MODE4 6 -#define LUT_FSL_READ 7 -#define LUT_FSL_WRITE 8 +#define LUT_READ 7 +#define LUT_WRITE 8 #define LUT_JMP_ON_CS 9 #define LUT_ADDR_DDR 10 #define LUT_MODE_DDR 11 #define LUT_MODE2_DDR 12 #define LUT_MODE4_DDR 13 -#define LUT_FSL_READ_DDR 14 -#define LUT_FSL_WRITE_DDR 15 +#define LUT_READ_DDR 14 +#define LUT_WRITE_DDR 15 #define LUT_DATA_LEARN 16 /* @@ -449,11 +449,6 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) } } - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); - /* Write enable */ lut_base = SEQID_WREN * 4; writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); @@ -462,11 +457,11 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) lut_base = SEQID_PP * 4; writel(LUT0(CMD, PAD1, nor->program_opcode) | LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); - writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); + writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); /* Read Status */ lut_base = SEQID_RDSR * 4; - writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1), + writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1), base + QUADSPI_LUT(lut_base)); /* Erase a sector */ @@ -481,17 +476,17 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* READ ID */ lut_base = SEQID_RDID * 4; - writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8), + writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8), base + QUADSPI_LUT(lut_base)); /* Write Register */ lut_base = SEQID_WRSR * 4; - writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2), + writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2), base + QUADSPI_LUT(lut_base)); /* Read Configuration Register */ lut_base = SEQID_RDCR * 4; - writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1), + writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1), base + QUADSPI_LUT(lut_base)); /* Write disable */ |