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authorColin Xu <colin.xu@intel.com>2019-02-14 12:56:33 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2019-02-18 17:19:11 +0800
commit2c7f9a4df9def07867087a520bc32169e2eec9f8 (patch)
treeb6c782e3494f3e76ac1433e790e8d6c72b82bcba /drivers
parent39c68e87bc50a71bcfe93582d9b0673ef30db418 (diff)
drm/i915/gvt: Use consist max display pipe numbers as i915 definition
GVT implements a homogeneous vGPU as host GPU so max vGPU display pipes can't exceed HW. The inconsistency definition has potential risks which could cause array indexing overflow. Remove the unnecessary define of INTEL_GVT_MAX_PIPE and align with i915. Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/gvt/gvt.h4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 0ba4b42e3bb0..db82a420efcc 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -111,11 +111,9 @@ struct intel_vgpu_cfg_space {
#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
-#define INTEL_GVT_MAX_PIPE 4
-
struct intel_vgpu_irq {
bool irq_warn_once[INTEL_GVT_EVENT_MAX];
- DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],
+ DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
INTEL_GVT_EVENT_MAX);
};