diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-08-25 20:50:07 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2016-08-25 20:53:24 +0800 |
| commit | fe38103d9e17a8595b0b13ca706a7b508c7762be (patch) | |
| tree | 19a427f05e803330dba642d737076071315b04d9 /drivers | |
| parent | af4b146c4bdfe282e8bca5ff2d43e9473afc878c (diff) | |
MLK-13119-3 cpufreq: imx6q: support VPU 396MHz
When VPU runs at 396MHz, VDDSOC_CAP's voltage
should be set to 1.275V for all set-points,
add VPU clock rate check to support this case.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/cpufreq/imx6q-cpufreq.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index eedbc417bf9f..ca0ae8ddfad1 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -292,11 +292,13 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) { struct device_node *np; struct dev_pm_opp *opp; + struct clk *vpu_axi_podf; unsigned long min_volt, max_volt; int num, ret; const struct property *prop; const __be32 *val; u32 nr, j, i = 0; + u32 vpu_axi_rate = 0; cpu_dev = get_cpu_device(0); if (!cpu_dev) { @@ -331,6 +333,10 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) secondary_sel = devm_clk_get(cpu_dev, "secondary_sel"); osc = devm_clk_get(cpu_dev, "osc"); + vpu_axi_podf = devm_clk_get(cpu_dev, "vpu_axi_podf"); + if (!IS_ERR(vpu_axi_podf)) + vpu_axi_rate = clk_get_rate(vpu_axi_podf); + arm_reg = devm_regulator_get_optional(cpu_dev, "arm"); pu_reg = devm_regulator_get_optional(cpu_dev, "pu"); soc_reg = devm_regulator_get(cpu_dev, "soc"); @@ -423,6 +429,13 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) imx6_soc_volt[soc_opp_count - 1] = 1250000; } #endif + if (vpu_axi_rate == 396000000) { + if (freq <= 996000) { + pr_info("increase SOC/PU voltage for VPU396MHz at %ld MHz\n", + freq / 1000); + imx6_soc_volt[soc_opp_count - 1] = 1275000; + } + } break; } } |