diff options
| author | Laurentiu Palcu <laurentiu.palcu@nxp.com> | 2018-09-05 16:12:41 +0300 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:33:52 +0800 |
| commit | dbbde931667ed425719c0985fcd6bff69d136990 (patch) | |
| tree | 17643a407bd4d5886d0357895d3341e89c221e9f /drivers | |
| parent | f099988bd36482cf3aea465377339413fd338761 (diff) | |
MLK-19460-1: drm: imx: dcss: lower CTXLD trigger IRQ threshold
Currently, the CTXLD IRQ trigger interrupt is set to 98% of the total
vertical frame lines. This leaves little room for interrupt handling
since the DB trigger point is set to 99%.
This patch moves the CTXLD IRQ trigger to 95%. Hence, if PM_QoS is
disabled, and A-53 cores are allowed to go to idle (hence slightly
bigger interrupt servicing time), we have enough time to handle the
interrupt and arm the CTLXD, before DB trigger point.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/imx/dcss/dcss-dtg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/imx/dcss/dcss-dtg.c b/drivers/gpu/imx/dcss/dcss-dtg.c index cf56ef1e038b..410f3c82054e 100644 --- a/drivers/gpu/imx/dcss/dcss-dtg.c +++ b/drivers/gpu/imx/dcss/dcss-dtg.c @@ -307,7 +307,7 @@ void dcss_dtg_sync_set(struct dcss_soc *dcss, struct videomode *vm) dcss_dtg_write(dtg, 0, DCSS_DTG_LINE0_INT); /* CTXLD trigger */ - dcss_dtg_write(dtg, ((98 * dis_lrc_y) / 100) << 16, DCSS_DTG_LINE1_INT); + dcss_dtg_write(dtg, ((95 * dis_lrc_y) / 100) << 16, DCSS_DTG_LINE0_INT); } EXPORT_SYMBOL(dcss_dtg_sync_set); |