diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2021-06-24 11:53:44 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2022-12-07 11:57:19 +0100 |
| commit | 241fdeb03d0b2948a50683b95d0e02219af55ec5 (patch) | |
| tree | c2d5565e73f507fe86177d768f58b0d9a8bede3e /drivers | |
| parent | 90e9ff9ce1803310606cf68c5d1c203e2c44ddca (diff) | |
imx8mp: native hdmi: allow pixelclocks being slightly off
The HDMI PHY driver currently can only generate a discrete set of
pixelclock frequencies. Any mode read from a monitor's EDID with a non
matching frequency is rejected.
Change that to find the closest possible frequency and accept the mode
if it deviates less than 6%. 6% is chosen as with that any pixelclock
in the range of 22.25Mhz - 297MHz should be accepted.
Related-to: ELB-4015
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit c6944a48583f6dc2d698df387fd648075491bf81)
Upstream-Status: Inappropriate [Downstream specific, i.MX 8M Plus HDMI subsystem not yet ready]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/imx/dw_hdmi-imx.c | 9 | ||||
| -rw-r--r-- | drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 18 |
2 files changed, 23 insertions, 4 deletions
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c index b08eae5278d0..3058268aceb5 100644 --- a/drivers/gpu/drm/imx/dw_hdmi-imx.c +++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c @@ -193,11 +193,16 @@ imx6dl_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, static bool imx8mp_hdmi_check_clk_rate(int rate_khz) { - int rate = rate_khz * 1000; + int rate; /* Check hdmi phy pixel clock support rate */ - if (rate != clk_round_rate(imx8mp_clocks[0].clk, rate)) + rate = clk_round_rate(imx8mp_clocks[0].clk, rate_khz * 1000); + /* Drop mode if pixelclk generated is more than 6% off */ + if ((rate < rate_khz * 940) || (rate > rate_khz * 1060)) { + pr_info("%s: mode with pixelclk %i kHz dropped\n", + __func__, rate_khz); return false; + } return true; } diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 532736aa23f6..94f3658e6ca7 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -926,8 +926,22 @@ static long samsung_hdmi_phy_clk_round_rate(struct clk_hw *hw, if (phy_cfg->clk_rate == rate) break; - if (phy_cfg->clk_rate == 0) - return -EINVAL; + if (phy_cfg->clk_rate == 0) { + /* If no exact setting found, try to find a close one */ + phy_cfg = samsung_phy_pll_cfg; + phy_cfg++; + for (; phy_cfg->clk_rate != 0; phy_cfg++) + if (phy_cfg->clk_rate > rate) + break; + + /* Bail out, no suitable setting found */ + if (phy_cfg->clk_rate == 0) + return -EINVAL; + + /* Use the next lower rate if that is closer to the wanted one */ + if ((phy_cfg->clk_rate - rate) > (rate - (phy_cfg-1)->clk_rate)) + phy_cfg--; + } return phy_cfg->clk_rate; } |