diff options
| author | Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com> | 2009-12-11 10:58:00 -0600 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2010-03-25 14:01:43 -0400 |
| commit | 13c7455b00358872522128268c1dde68fe2f246f (patch) | |
| tree | c646f1330b7a139334bdb0f43c768f8c97f44c6e /drivers | |
| parent | 1783a9f893310d9a7b1ef2764fc8ac0c3d71aeb3 (diff) | |
ENGR00119263: MX51 : Fix pll_set_rate function
pll_set_rate function should only wait for PLL relock if PLL is enabled.
Also add a timeout to the infinte loop.
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mxc/ipu3/ipu_common.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index 5d90d47e34b9..56657b8f6ea1 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -212,7 +212,7 @@ static void _ipu_pixel_clk_disable(struct clk *clk) static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) { - u32 di_gen = 0;/*__raw_readl(DI_GENERAL(clk->id));*/ + u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); if (parent == g_ipu_clk) di_gen &= ~DI_GEN_DI_CLK_EXT; |