LF-1278:[8QM_MEK/8QXP_MEK]mxc:vpu_windsor: implement ctrl to set h264 aspect ratio

The default aspect ratio supplied by firmware may be not correct.
And V4L2 have some ctrl interface to set it.
	V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE,
	V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC,
	V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH,
	V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT
So driver can implement these controls and supply a proper default value
vpu_windsor driver 1.0.3

Signed-off-by: Ming Qian <ming.qian@nxp.com>
Reviewed-by: Shijie Qin <shijie.qin@nxp.com>

4 files changed, 188 insertions, 7 deletions

diff --git a/drivers/mxc/vpu_windsor/vpu_encoder_b0.c b/drivers/mxc/vpu_windsor/vpu_encoder_b0.c
index b895e7f1f4cc..a50b32f65082 100644
--- a/drivers/mxc/vpu_windsor/vpu_encoder_b0.c
+++ b/drivers/mxc/vpu_windsor/vpu_encoder_b0.c
@@ -57,7 +57,7 @@
 #include "vpu_encoder_mu.h"
 #include "vpu_encoder_pm.h"
 
-#define VPU_ENC_DRIVER_VERSION		"1.0.2"
+#define VPU_ENC_DRIVER_VERSION		"1.0.3"
 
 struct vpu_frame_info {
 	struct list_head list;
@@ -2764,11 +2764,44 @@ static int handle_event_start_done(struct vpu_ctx *ctx)
 	return 0;
 }
 
+static void vpu_enc_config_expert_mode_parm(struct vpu_ctx *ctx)
+{
+	struct vpu_attr *attr = NULL;
+	pMEDIAIP_ENC_EXPERT_MODE_PARAM param = NULL;
+
+	if (!ctx)
+		return;
+
+	attr = get_vpu_ctx_attr(ctx);
+	if (!attr)
+		return;
+
+	param = get_rpc_expert_mode_param(ctx);
+	if (!param)
+		return;
+
+	param->Config.frame_rate_num = attr->fival.numerator;
+	param->Config.frame_rate_den = attr->fival.denominator;
+	vpu_dbg(LVL_FLOW, "[%d:%d] h264 frame rate: %d/%d\n",
+		ctx->core_dev->id, ctx->str_index,
+		param->Config.frame_rate_num, param->Config.frame_rate_den);
+
+	param->Config.h264_aspect_ratio_present = attr->h264_vui_sar_enable;
+	param->Config.aspect_ratio = attr->h264_vui_sar_idc;
+	param->Config.h264_aspect_ratio_sar_width = attr->h264_vui_sar_width;
+	param->Config.h264_aspect_ratio_sar_height = attr->h264_vui_sar_height;
+	vpu_dbg(LVL_FLOW,
+		"[%d:%d] h264 vui sar:enable=%d, idc=%d, width=%d, height=%d\n",
+		ctx->core_dev->id, ctx->str_index,
+		attr->h264_vui_sar_enable,
+		attr->h264_vui_sar_idc,
+		attr->h264_vui_sar_width,
+		attr->h264_vui_sar_height);
+}
+
 static int handle_event_mem_request(struct vpu_ctx *ctx,
 				MEDIAIP_ENC_MEM_REQ_DATA *req_data)
 {
-	pMEDIAIP_ENC_EXPERT_MODE_PARAM pEncExpertModeParam = NULL;
-	struct vpu_attr *attr = NULL;
 	int ret;
 
 	if (!ctx || !req_data)
@@ -2779,10 +2812,9 @@ static int handle_event_mem_request(struct vpu_ctx *ctx,
 		vpu_err("fail to alloc encoder memory\n");
 		return ret;
 	}
-	pEncExpertModeParam = get_rpc_expert_mode_param(ctx);
-	attr = get_vpu_ctx_attr(ctx);
-	pEncExpertModeParam->Config.frame_rate_num = attr->fival.numerator;
-	pEncExpertModeParam->Config.frame_rate_den = attr->fival.denominator;
+
+	vpu_enc_config_expert_mode_parm(ctx);
+
 	vpu_ctx_send_cmd(ctx, GTB_ENC_CMD_STREAM_START, 0, NULL);
 	set_bit(VPU_ENC_STATUS_START_SEND, &ctx->status);
 	vpu_dbg(LVL_FLOW, "[%d:%d] start stream\n",
diff --git a/drivers/mxc/vpu_windsor/vpu_encoder_b0.h b/drivers/mxc/vpu_windsor/vpu_encoder_b0.h
index 709dc88aac9a..c989e1b4f645 100644
--- a/drivers/mxc/vpu_windsor/vpu_encoder_b0.h
+++ b/drivers/mxc/vpu_windsor/vpu_encoder_b0.h
@@ -261,6 +261,10 @@ struct vpu_attr {
 	struct vpu_statistic statistic;
 	MEDIAIP_ENC_PARAM param;
 	struct v4l2_fract fival;
+	u32 h264_vui_sar_enable;
+	u32 h264_vui_sar_idc;
+	u32 h264_vui_sar_width;
+	u32 h264_vui_sar_height;
 
 	unsigned long ts_start[2];
 	unsigned long msg_count;
diff --git a/drivers/mxc/vpu_windsor/vpu_encoder_config.h b/drivers/mxc/vpu_windsor/vpu_encoder_config.h
index 306fa9ea3b21..8f977b9bf629 100644
--- a/drivers/mxc/vpu_windsor/vpu_encoder_config.h
+++ b/drivers/mxc/vpu_windsor/vpu_encoder_config.h
@@ -48,4 +48,6 @@
 #define VPU_ENC_SEQ_CAPACITY		32
 #define VPU_ENC_INVALID_TIMESTAMP	-1
 
+#define VPU_ENC_H264_EXTENDED_SAR	255
+
 #endif
diff --git a/drivers/mxc/vpu_windsor/vpu_encoder_ctrl.c b/drivers/mxc/vpu_windsor/vpu_encoder_ctrl.c
index bd43587c5c2a..fc7f0ce126ec 100644
--- a/drivers/mxc/vpu_windsor/vpu_encoder_ctrl.c
+++ b/drivers/mxc/vpu_windsor/vpu_encoder_ctrl.c
@@ -264,6 +264,64 @@ static int set_h264_cpb_size(struct v4l2_ctrl *ctrl)
 	return 0;
 }
 
+static int set_h264_vui_sar_enable(struct v4l2_ctrl *ctrl)
+{
+	struct vpu_ctx *ctx = v4l2_ctrl_to_ctx(ctrl);
+	struct vpu_attr *attr = get_vpu_ctx_attr(ctx);
+
+	vpu_dbg(LVL_CTRL, "set h264 vui sar enable %d\n", ctrl->val);
+	mutex_lock(&ctx->instance_mutex);
+	if (ctrl->val)
+		attr->h264_vui_sar_enable = 1;
+	else
+		attr->h264_vui_sar_enable = 0;
+	mutex_unlock(&ctx->instance_mutex);
+
+	return 0;
+}
+
+static int set_h264_vui_sar_idc(struct v4l2_ctrl *ctrl)
+{
+	struct vpu_ctx *ctx = v4l2_ctrl_to_ctx(ctrl);
+	struct vpu_attr *attr = get_vpu_ctx_attr(ctx);
+
+	vpu_dbg(LVL_CTRL, "set h264 vui sar idc %d\n", ctrl->val);
+	mutex_lock(&ctx->instance_mutex);
+	if (ctrl->val < V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED)
+		attr->h264_vui_sar_idc = ctrl->val;
+	else
+		attr->h264_vui_sar_idc = VPU_ENC_H264_EXTENDED_SAR;
+	mutex_unlock(&ctx->instance_mutex);
+
+	return 0;
+}
+
+static int set_h264_vui_sar_width(struct v4l2_ctrl *ctrl)
+{
+	struct vpu_ctx *ctx = v4l2_ctrl_to_ctx(ctrl);
+	struct vpu_attr *attr = get_vpu_ctx_attr(ctx);
+
+	vpu_dbg(LVL_CTRL, "set h264 vui sar width %d\n", ctrl->val);
+	mutex_lock(&ctx->instance_mutex);
+	attr->h264_vui_sar_width = ctrl->val;
+	mutex_unlock(&ctx->instance_mutex);
+
+	return 0;
+}
+
+static int set_h264_vui_sar_height(struct v4l2_ctrl *ctrl)
+{
+	struct vpu_ctx *ctx = v4l2_ctrl_to_ctx(ctrl);
+	struct vpu_attr *attr = get_vpu_ctx_attr(ctx);
+
+	vpu_dbg(LVL_CTRL, "set h264 vui sar height %d\n", ctrl->val);
+	mutex_lock(&ctx->instance_mutex);
+	attr->h264_vui_sar_height = ctrl->val;
+	mutex_unlock(&ctx->instance_mutex);
+
+	return 0;
+}
+
 static int add_ctrl_h264_profile(struct vpu_ctx *ctx)
 {
 	static const struct v4l2_ctrl_ops ctrl_h264_profile_ops = {
@@ -595,6 +653,87 @@ static int add_ctrl_h264_cpb_size(struct vpu_ctx *ctx)
 	return 0;
 }
 
+static int add_ctrl_h264_vui_sar_enable(struct vpu_ctx *ctx)
+{
+	static const struct v4l2_ctrl_ops ctrl_vui_sar_enable_ops = {
+		.s_ctrl = set_h264_vui_sar_enable,
+	};
+	struct v4l2_ctrl *ctrl;
+
+	ctrl = v4l2_ctrl_new_std(&ctx->ctrl_handler,
+				&ctrl_vui_sar_enable_ops,
+				V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE,
+				0, 1, 1, 1);
+	if (!ctrl) {
+		vpu_err("add ctrl h264 vui sar enable fail\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int add_ctrl_h264_vui_sar_idc(struct vpu_ctx *ctx)
+{
+	static const struct v4l2_ctrl_ops ctrl_vui_sar_idc_ops = {
+		.s_ctrl = set_h264_vui_sar_idc,
+	};
+	struct v4l2_ctrl *ctrl;
+
+	ctrl = v4l2_ctrl_new_std_menu(&ctx->ctrl_handler,
+				&ctrl_vui_sar_idc_ops,
+				V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC,
+				V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED,
+				0x0,
+				V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1);
+
+
+	if (!ctrl) {
+		vpu_err("add ctrl h264 vui sar idc fail\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int add_ctrl_h264_vui_sar_width(struct vpu_ctx *ctx)
+{
+	static const struct v4l2_ctrl_ops ctrl_vui_sar_width_ops = {
+		.s_ctrl = set_h264_vui_sar_width,
+	};
+	struct v4l2_ctrl *ctrl;
+
+	ctrl = v4l2_ctrl_new_std(&ctx->ctrl_handler,
+				&ctrl_vui_sar_width_ops,
+				V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH,
+				0, USHRT_MAX, 1, 1);
+
+	if (!ctrl) {
+		vpu_err("add ctrl h264 vui sar width fail\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int add_ctrl_h264_vui_sar_height(struct vpu_ctx *ctx)
+{
+	static const struct v4l2_ctrl_ops ctrl_vui_sar_height_ops = {
+		.s_ctrl = set_h264_vui_sar_height,
+	};
+	struct v4l2_ctrl *ctrl;
+
+	ctrl = v4l2_ctrl_new_std(&ctx->ctrl_handler,
+				&ctrl_vui_sar_height_ops,
+				V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT,
+				0, USHRT_MAX, 1, 1);
+	if (!ctrl) {
+		vpu_err("add ctrl h264 vui sar height fail\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int vpu_enc_register_ctrls(struct vpu_ctx *ctx)
 {
 	add_ctrl_h264_profile(ctx);
@@ -612,6 +751,10 @@ static int vpu_enc_register_ctrls(struct vpu_ctx *ctx)
 	add_ctrl_display_re_ordering(ctx);
 	add_ctrl_force_key_frame(ctx);
 	add_ctrl_h264_cpb_size(ctx);
+	add_ctrl_h264_vui_sar_enable(ctx);
+	add_ctrl_h264_vui_sar_idc(ctx);
+	add_ctrl_h264_vui_sar_width(ctx);
+	add_ctrl_h264_vui_sar_height(ctx);
 
 	return 0;
 }