diff options
author | Tony Lin <tony.lin@freescale.com> | 2011-08-31 13:22:51 +0800 |
---|---|---|
committer | Tony Lin <tony.lin@freescale.com> | 2011-09-01 10:42:06 +0800 |
commit | 37e7b1c5dd2f3a509cd02d9c53deaa2aa4079c98 (patch) | |
tree | 88058234da5bb8bb42cdbe853309395a192517da /drivers | |
parent | 2ecbb95c0d3e6fcefae3a0bf9800f9149adec824 (diff) |
ENGR00155611 [mx6q]correct eMMC DDR mode clock setting
in uSDHC controller, SDCLKFS field in SYS_CTRL register
is defined differently from eSDHC
In Single Data Rate mode(DDR_EN bit of MIXERCTRL is '0')
Only the following settings are allowed:
80h) Base clock divided by 256
40h) Base clock divided by 128
20h) Base clock divided by 64
10h) Base clock divided by 32
08h) Base clock divided by 16
04h) Base clock divided by 8
02h) Base clock divided by 4
01h) Base clock divided by 2
00h) Base clock divided by 1
While in Dual Data Rate mode(DDR_EN bit of MIXERCTRL is '1')
Only the following settings are allowed:
80h) Base clock divided by 512
40h) Base clock divided by 256
20h) Base clock divided by 128
10h) Base clock divided by 64
08h) Base clock divided by 32
04h) Base clock divided by 16
02h) Base clock divided by 8
01h) Base clock divided by 4
00h) Base clock divided by 2
so the clock setting function should be changed to fit the definition
Signed-off-by: Tony Lin <tony.lin@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mmc/host/sdhci-esdhc-imx.c | 6 | ||||
-rw-r--r-- | drivers/mmc/host/sdhci-esdhc.h | 16 |
2 files changed, 18 insertions, 4 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 63c96aa2a1f9..5c6d8f58bcf0 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -31,8 +31,7 @@ /* VENDOR SPEC register */ #define SDHCI_VENDOR_SPEC 0xC0 #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 -#define SDHCI_MIX_CTRL 0x48 -#define SDHCI_MIX_CTRL_DDREN (1 << 3) + #define SDHCI_MIX_CTRL_EXE_TUNE (1 << 22) #define SDHCI_MIX_CTRL_SMPCLK_SEL (1 << 23) #define SDHCI_MIX_CTRL_AUTO_TUNE (1 << 24) @@ -340,6 +339,9 @@ static int plt_ddr_mode(struct sdhci_host *host, int mode) sdhci_writel(host, reg, SDHCI_MIX_CTRL); + /* set clock frequency again */ + esdhc_set_clock(host, host->clock); + return 0; } diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h index 62e50ef3121f..c4e8fad4d999 100644 --- a/drivers/mmc/host/sdhci-esdhc.h +++ b/drivers/mmc/host/sdhci-esdhc.h @@ -42,14 +42,26 @@ #define ESDHC_HOST_CONTROL_RES 0x05 +#define SDHCI_MIX_CTRL 0x48 +#define SDHCI_MIX_CTRL_DDREN (1 << 3) + static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) { int pre_div = 2; int div = 1; u32 temp; + struct esdhc_platform_data *boarddata; + int ddr_mode = 0; - if (cpu_is_mx6q()) + boarddata = host->mmc->parent->platform_data; + if (cpu_is_mx6q()) { pre_div = 1; + if (readl(host->ioaddr + SDHCI_MIX_CTRL) & + SDHCI_MIX_CTRL_DDREN) { + ddr_mode = 1; + pre_div = 2; + } + } temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); @@ -67,7 +79,7 @@ static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", clock, host->max_clk / pre_div / div); - pre_div >>= 1; + pre_div >>= (1 + ddr_mode); div--; temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |