crypto: tegra-aes: code refactor

- reset intr_status if error occur while encrypt/decrypt
- rename iram variables to _phys and _virt
- use bsea for rng
- remove unwanted macros from the header file

Bug 833165
Bug 778258

Reviewed-on: http://git-master/r/35830
(cherry picked from commit b3c905c825c16cfff9fe43681f616aa4a0314a8d)

Change-Id: I4c76bc87ae4dbf5cab7a49ff070cf95323124537
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/41509
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

2 files changed, 54 insertions, 71 deletions

diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c
index 239d74dbbb9c..2d46ed8fc29a 100644
--- a/drivers/crypto/tegra-aes.c
+++ b/drivers/crypto/tegra-aes.c
@@ -151,6 +151,8 @@ struct tegra_aes_engine {
 	void __iomem *io_base;
 	void __iomem *ivkey_base;
 	unsigned long phys_base;
+	unsigned long iram_phys;
+	void *iram_virt;
 	dma_addr_t ivkey_phys_base;
 	dma_addr_t dma_buf_in;
 	dma_addr_t dma_buf_out;
@@ -176,8 +178,6 @@ struct tegra_aes_dev {
 	struct tegra_aes_engine bsea;
 	struct nvmap_client *client;
 	struct nvmap_handle_ref *h_ref;
-	unsigned long bsea_iram_address;
-	void *bsea_iram_base;
 	struct tegra_aes_ctx *ctx;
 	struct crypto_queue queue;
 	spinlock_t lock;
@@ -223,12 +223,13 @@ static inline void aes_writel(struct tegra_aes_engine *engine,
 	writel(val, engine->io_base + offset);
 }
 
-static int bsea_alloc_iram(struct tegra_aes_dev *dd)
+static int alloc_iram(struct tegra_aes_dev *dd)
 {
 	size_t size, align ;
 	int err;
 
 	dd->h_ref = NULL;
+
 	/* [key+iv+u-iv=64B] * 8 = 512Bytes */
 	size = align = (AES_HW_KEY_TABLE_LENGTH_BYTES * AES_NR_KEYSLOTS);
 	dd->client = nvmap_create_client(nvmap_dev, "aes_bsea");
@@ -251,22 +252,22 @@ static int bsea_alloc_iram(struct tegra_aes_dev *dd)
 		nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
 		goto out;
 	}
-	dd->bsea_iram_address = nvmap_handle_address(dd->client,
+	dd->bsea.iram_phys = nvmap_handle_address(dd->client,
 					nvmap_ref_to_id(dd->h_ref));
 
-	dd->bsea_iram_base = nvmap_mmap(dd->h_ref);	/* get virtual address */
-	if (!dd->bsea_iram_base) {
+	dd->bsea.iram_virt = nvmap_mmap(dd->h_ref);	/* get virtual address */
+	if (!dd->bsea.iram_virt) {
 		dev_err(dd->dev, "%s: no mem, BSEA IRAM alloc failure\n",
 		__func__);
 		goto out;
 	}
-	memset(dd->bsea_iram_base, 0, dd->h_ref->handle->size);
+	memset(dd->bsea.iram_virt, 0, dd->h_ref->handle->size);
 
 	return 0;
 
 out:
-	if (dd->bsea_iram_base)
-		nvmap_munmap(dd->h_ref, dd->bsea_iram_base);
+	if (dd->bsea.iram_virt)
+		nvmap_munmap(dd->h_ref, dd->bsea.iram_virt);
 
 	if (dd->client) {
 		nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
@@ -276,10 +277,10 @@ out:
 	return -ENOMEM;
 }
 
-static void bsea_free_iram(struct tegra_aes_dev *dd)
+static void free_iram(struct tegra_aes_dev *dd)
 {
-	if (dd->bsea_iram_base)
-		nvmap_munmap(dd->h_ref, dd->bsea_iram_base);
+	if (dd->bsea.iram_virt)
+		nvmap_munmap(dd->h_ref, dd->bsea.iram_virt);
 
 	if (dd->client) {
 		nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
@@ -346,7 +347,7 @@ static int aes_start_crypt(struct tegra_aes_engine *eng, u32 in_addr,
 	/* access SDRAM through AHB */
 	value &= (~CMDQ_CTRL_SRC_STM_SEL_FIELD & ~CMDQ_CTRL_DST_STM_SEL_FIELD);
 	value |= (CMDQ_CTRL_SRC_STM_SEL_FIELD | CMDQ_CTRL_DST_STM_SEL_FIELD |
-		CMDQ_CTRL_ICMDQEN_FIELD);
+		CMDQ_CTRL_ICMDQEN_FIELD | CMDQ_CTRL_ERROR_FLUSH_ENB);
 	aes_writel(eng, value, CMDQUE_CONTROL);
 
 	value = 0;
@@ -513,7 +514,7 @@ static int aes_set_key(struct tegra_aes_engine *eng)
 			UCQCMD_CRYPTO_TABLESEL << ICQBITSHIFT_TABLESEL |
 			(UCQCMD_KEYTABLESEL | eng->slot_num)
 			<< ICQBITSHIFT_KEYTABLEID |
-			dd->bsea_iram_address >> 2;
+			dd->bsea.iram_phys >> 2;
 			aes_writel(eng, value, ICMDQUE_WR);
 		do {
 			value = aes_readl(eng, INTR_STATUS);
@@ -687,9 +688,9 @@ static int tegra_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 
 		/* copy the key */
 		memset(dd->bsev.ivkey_base, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
-		memset(dd->bsea_iram_base, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
+		memset(dd->bsea.iram_virt, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
 		memcpy(dd->bsev.ivkey_base, key, keylen);
-		memcpy(dd->bsea_iram_base, key, keylen);
+		memcpy(dd->bsea.iram_virt, key, keylen);
 	} else {
 		dd->bsev.slot_num = SSK_SLOT_NUM;
 		dd->bsea.slot_num = SSK_SLOT_NUM;
@@ -738,22 +739,20 @@ static void bsea_workqueue_handler(struct work_struct *work)
 	aes_hw_deinit(engine);
 }
 
+#define INT_ERROR_MASK	0xFFF000
 static irqreturn_t aes_bsev_irq(int irq, void *dev_id)
 {
 	struct tegra_aes_dev *dd = (struct tegra_aes_dev *)dev_id;
 	u32 value = aes_readl(&dd->bsev, INTR_STATUS);
-	u32 intr_err_mask = (value & (BIT(19) | BIT(20) | BIT(22)));
 
-	dev_dbg(dd->dev, "irq_stat: 0x%x", value);
-	if (intr_err_mask) {
-		aes_writel(&dd->bsea, intr_err_mask, INTR_STATUS);
-		goto done;
-	}
+	dev_dbg(dd->dev, "bsev irq_stat: 0x%x", value);
+	if (value & INT_ERROR_MASK)
+		aes_writel(&dd->bsev, INT_ERROR_MASK, INTR_STATUS);
 
+	value = aes_readl(&dd->bsev, INTR_STATUS);
 	if (!(value & ENGINE_BUSY_FIELD))
 		complete(&dd->bsev.op_complete);
 
-done:
 	return IRQ_HANDLED;
 }
 
@@ -761,18 +760,15 @@ static irqreturn_t aes_bsea_irq(int irq, void *dev_id)
 {
 	struct tegra_aes_dev *dd = (struct tegra_aes_dev *)dev_id;
 	u32 value = aes_readl(&dd->bsea, INTR_STATUS);
-	u32 intr_err_mask = (value & (BIT(19) | BIT(20) | BIT(22)));
 
-	dev_dbg(dd->dev, "irq_stat: 0x%x", value);
-	if (intr_err_mask) {
-		aes_writel(&dd->bsea, intr_err_mask, INTR_STATUS);
-		goto done;
-	}
+	dev_dbg(dd->dev, "bsea irq_stat: 0x%x", value);
+	if (value & INT_ERROR_MASK)
+		aes_writel(&dd->bsea, INT_ERROR_MASK, INTR_STATUS);
 
+	value = aes_readl(&dd->bsea, INTR_STATUS);
 	if (!(value & ENGINE_BUSY_FIELD))
 		complete(&dd->bsea.op_complete);
 
-done:
 	return IRQ_HANDLED;
 }
 
@@ -837,7 +833,7 @@ static int tegra_aes_get_random(struct crypto_rng *tfm, u8 *rdata,
 	unsigned int dlen)
 {
 	struct tegra_aes_dev *dd = aes_dev;
-	struct tegra_aes_engine *eng = &dd->bsev;
+	struct tegra_aes_engine *eng = &dd->bsea;
 	int ret, i;
 	u8 *dest = rdata, *dt = dd->dt;
 
@@ -894,7 +890,7 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed,
 {
 	struct tegra_aes_dev *dd = aes_dev;
 	struct tegra_aes_ctx *ctx = &rng_ctx;
-	struct tegra_aes_engine *eng = &dd->bsev;
+	struct tegra_aes_engine *eng = &dd->bsea;
 	struct tegra_aes_slot *key_slot;
 	struct timespec ts;
 	int ret = 0;
@@ -927,8 +923,8 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed,
 	}
 
 	/* copy the key to the key slot */
-	memset(eng->ivkey_base, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
-	memcpy(eng->ivkey_base, seed + DEFAULT_RNG_BLK_SZ, AES_KEYSIZE_128);
+	memset(dd->bsea.iram_virt, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
+	memcpy(dd->bsea.iram_virt, seed + DEFAULT_RNG_BLK_SZ, AES_KEYSIZE_128);
 
 	/* take the hardware semaphore */
 	if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
@@ -1124,7 +1120,7 @@ static int tegra_aes_probe(struct platform_device *pdev)
 		goto out;
 	}
 
-	err = bsea_alloc_iram(dd);
+	err = alloc_iram(dd);
 	if (err < 0) {
 		dev_err(dev, "Failed to allocate IRAM for BSEA\n");
 		goto out;
@@ -1264,7 +1260,8 @@ out:
 	for (j = 0; j < i; j++)
 		crypto_unregister_alg(&algs[j]);
 
-	bsea_free_iram(dd);
+	free_iram(dd);
+
 	if (dd->bsev.ivkey_base) {
 		dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base,
 			dd->bsev.ivkey_phys_base);
@@ -1344,7 +1341,7 @@ static int __devexit tegra_aes_remove(struct platform_device *pdev)
 	for (i = 0; i < ARRAY_SIZE(algs); i++)
 		crypto_unregister_alg(&algs[i]);
 
-	bsea_free_iram(dd);
+	free_iram(dd);
 	dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base,
 		dd->bsev.ivkey_phys_base);
 	dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsev.buf_in,
diff --git a/drivers/crypto/tegra-aes.h b/drivers/crypto/tegra-aes.h
index 9c53fe4165cc..45696467cdfc 100644
--- a/drivers/crypto/tegra-aes.h
+++ b/drivers/crypto/tegra-aes.h
@@ -44,52 +44,39 @@
 #define SECURE_SEC_SEL7		0x115C
 
 /* interrupt status reg masks and shifts */
-#define DMA_BUSY_SHIFT	9
-#define DMA_BUSY_FIELD	(0x1 << DMA_BUSY_SHIFT)
-#define ICQ_EMPTY_SHIFT	3
-#define ICQ_EMPTY_FIELD	(0x1 << ICQ_EMPTY_SHIFT)
-#define ENGINE_BUSY_SHIFT	0
-#define ENGINE_BUSY_FIELD	(0x1 << ENGINE_BUSY_SHIFT)
+#define DMA_BUSY_FIELD		BIT(9)
+#define ICQ_EMPTY_FIELD		BIT(3)
+#define ENGINE_BUSY_FIELD	BIT(0)
 
 /* secure select reg masks and shifts */
-#define SECURE_SEL0_KEYREAD_ENB0_SHIFT	0
-#define SECURE_SEL0_KEYREAD_ENB0_FIELD	(0x1 << SECURE_SEL0_KEYREAD_ENB0_SHIFT)
+#define SECURE_SEL0_KEYREAD_ENB0_FIELD	BIT(0)
 
 /* secure config ext masks and shifts */
-#define SECURE_KEY_SCH_DIS_SHIFT	15
-#define SECURE_KEY_SCH_DIS_FIELD	(0x1 << SECURE_KEY_SCH_DIS_SHIFT)
+#define SECURE_KEY_SCH_DIS_FIELD	BIT(15)
 
 /* secure config masks and shifts */
 #define SECURE_KEY_INDEX_SHIFT		20
 #define SECURE_KEY_INDEX_FIELD		(0x1F << SECURE_KEY_INDEX_SHIFT)
-#define SECURE_BLOCK_CNT_SHIFT		0
-#define SECURE_BLOCK_CNT_FIELD		(0xFFFFF << SECURE_BLOCK_CNT_SHIFT)
+#define SECURE_BLOCK_CNT_FIELD		(0xFFFFF)
 
 /* stream interface select masks and shifts */
-#define CMDQ_CTRL_SRC_STM_SEL_SHIFT	4
-#define CMDQ_CTRL_SRC_STM_SEL_FIELD	(1 << CMDQ_CTRL_SRC_STM_SEL_SHIFT)
-#define CMDQ_CTRL_DST_STM_SEL_SHIFT	5
-#define CMDQ_CTRL_DST_STM_SEL_FIELD	(1 << CMDQ_CTRL_DST_STM_SEL_SHIFT)
-#define CMDQ_CTRL_ICMDQEN_SHIFT		1
-#define CMDQ_CTRL_ICMDQEN_FIELD		(1 << CMDQ_CTRL_ICMDQEN_SHIFT)
-#define CMDQ_CTRL_UCMDQEN_SHIFT		0
-#define CMDQ_CTRL_UCMDQEN_FIELD		(1 << CMDQ_CTRL_UCMDQEN_SHIFT)
+#define CMDQ_CTRL_DST_STM_SEL_FIELD	BIT(5)
+#define CMDQ_CTRL_SRC_STM_SEL_FIELD	BIT(4)
+#define CMDQ_CTRL_ERROR_FLUSH_ENB	BIT(2)
+#define CMDQ_CTRL_ICMDQEN_FIELD		BIT(1)
+#define CMDQ_CTRL_UCMDQEN_FIELD		BIT(0)
 
 /* config regsiter masks and shifts */
-#define CONFIG_ENDIAN_ENB_SHIFT		10
-#define CONFIG_ENDIAN_ENB_FIELD		(0x1 << CONFIG_ENDIAN_ENB_SHIFT)
-#define CONFIG_MODE_SEL_SHIFT		0
-#define CONFIG_MODE_SEL_FIELD		(0x1F << CONFIG_MODE_SEL_SHIFT)
+#define CONFIG_ENDIAN_ENB_FIELD		BIT(10)
+#define CONFIG_MODE_SEL_FIELD		BIT(0)
 
 /* extended config */
-#define SECURE_OFFSET_CNT_SHIFT		24
-#define SECURE_OFFSET_CNT_FIELD		(0xFF << SECURE_OFFSET_CNT_SHIFT)
-#define SECURE_KEYSCHED_GEN_SHIFT	15
-#define SECURE_KEYSCHED_GEN_FIELD	(1 << SECURE_KEYSCHED_GEN_SHIFT)
+#define SECURE_OFFSET_CNT_FIELD		(0xFF << 24)
+#define SECURE_KEYSCHED_GEN_FIELD	BIT(15)
 
 /* init vector select */
 #define SECURE_IV_SELECT_SHIFT		10
-#define SECURE_IV_SELECT_FIELD		(1 << SECURE_IV_SELECT_SHIFT)
+#define SECURE_IV_SELECT_FIELD		BIT(10)
 
 /* secure engine input */
 #define SECURE_INPUT_ALG_SEL_SHIFT	28
@@ -97,9 +84,9 @@
 #define SECURE_INPUT_KEY_LEN_SHIFT	16
 #define SECURE_INPUT_KEY_LEN_FIELD	(0xFFF << SECURE_INPUT_KEY_LEN_SHIFT)
 #define SECURE_RNG_ENB_SHIFT		11
-#define SECURE_RNG_ENB_FIELD		(0x1 << SECURE_RNG_ENB_SHIFT)
+#define SECURE_RNG_ENB_FIELD		BIT(11)
 #define SECURE_CORE_SEL_SHIFT		9
-#define SECURE_CORE_SEL_FIELD		(0x1 << SECURE_CORE_SEL_SHIFT)
+#define SECURE_CORE_SEL_FIELD		BIT(9)
 #define SECURE_VCTRAM_SEL_SHIFT		7
 #define SECURE_VCTRAM_SEL_FIELD		(0x3 << SECURE_VCTRAM_SEL_SHIFT)
 #define SECURE_INPUT_SEL_SHIFT		5
@@ -107,8 +94,7 @@
 #define SECURE_XOR_POS_SHIFT		3
 #define SECURE_XOR_POS_FIELD		(0x3 << SECURE_XOR_POS_SHIFT)
 #define SECURE_HASH_ENB_SHIFT		2
-#define SECURE_HASH_ENB_FIELD		(0x1 << SECURE_HASH_ENB_SHIFT)
-#define SECURE_ON_THE_FLY_SHIFT		0
-#define SECURE_ON_THE_FLY_FIELD		(1 << SECURE_ON_THE_FLY_SHIFT)
+#define SECURE_HASH_ENB_FIELD		BIT(2)
+#define SECURE_ON_THE_FLY_FIELD		BIT(0)
 
 #endif