diff options
| author | Wei WANG <wei_wang@realsil.com.cn> | 2013-01-29 15:21:35 +0800 |
|---|---|---|
| committer | Samuel Ortiz <sameo@linux.intel.com> | 2013-02-14 00:22:57 +0100 |
| commit | 678cacdfda800b0cdbfdd01350dcf5e3b767f6ed (patch) | |
| tree | 746389666f65c5130935e618651ffc9190a5b39a /drivers | |
| parent | f84ef04227d8983c8f76ac0f5cf8b0a15e0c67af (diff) | |
mfd: rtsx: Fix checkpatch warning
WARNING: Avoid CamelCase: <min_N>
+ u8 N, min_N, max_N, clk_divider;
WARNING: Avoid CamelCase: <max_N>
+ u8 N, min_N, max_N, clk_divider;
Signed-off-by: Wei WANG <wei_wang@realsil.com.cn>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mfd/rtsx_pcr.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c index b2cfd2ed616c..4897c39cfb7b 100644 --- a/drivers/mfd/rtsx_pcr.c +++ b/drivers/mfd/rtsx_pcr.c @@ -590,7 +590,7 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) { int err, clk; - u8 N, min_N, max_N, clk_divider; + u8 n, min_n, max_n, clk_divider; u8 mcu_cnt, div, max_div; u8 depth[] = { [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, @@ -615,8 +615,8 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, card_clock /= 1000000; dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock); - min_N = 80; - max_N = 208; + min_n = 80; + max_n = 208; max_div = CLK_DIV_8; clk = card_clock; @@ -630,30 +630,30 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, return 0; if (pcr->ops->conv_clk_and_div_n) - N = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); + n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); else - N = (u8)(clk - 2); - if ((clk <= 2) || (N > max_N)) + n = (u8)(clk - 2); + if ((clk <= 2) || (n > max_n)) return -EINVAL; mcu_cnt = (u8)(125/clk + 3); if (mcu_cnt > 15) mcu_cnt = 15; - /* Make sure that the SSC clock div_n is equal or greater than min_N */ + /* Make sure that the SSC clock div_n is equal or greater than min_n */ div = CLK_DIV_1; - while ((N < min_N) && (div < max_div)) { + while ((n < min_n) && (div < max_div)) { if (pcr->ops->conv_clk_and_div_n) { - int dbl_clk = pcr->ops->conv_clk_and_div_n(N, + int dbl_clk = pcr->ops->conv_clk_and_div_n(n, DIV_N_TO_CLK) * 2; - N = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, + n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, CLK_TO_DIV_N); } else { - N = (N + 2) * 2 - 2; + n = (n + 2) * 2 - 2; } div++; } - dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div); + dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div); ssc_depth = depth[ssc_depth]; if (double_clk) @@ -670,7 +670,7 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, SSC_DEPTH_MASK, ssc_depth); - rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N); + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); if (vpclk) { rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, |