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authorJason Chen <b02280@freescale.com>2009-10-19 14:15:16 +0800
committerJason Chen <b02280@freescale.com>2009-10-19 14:15:16 +0800
commit6d5a36ac42b91d0b2158c6d77c33d0ed29cd3e7b (patch)
tree8c2617e71dfe5736c2dcade5a2d23cbb3b13783a /drivers
parent1444395a93b3f9f91de07e3abe14ddd8a0f9a9b0 (diff)
ENGR00117388 ipuv3: Futher fix for diable IPU channel
IPU channel disable should wait all channels finish busy state, should wait for input dma interrupt first then output dma interrupt as the correct sequence for all channels. This patch fix the DQ_BUF fail issue in VPU unit test. Signed-off-by: Jason Chen <b02280@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mxc/ipu3/ipu_common.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index 34aca0fae5e4..4c46db8b0abc 100644
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -1671,16 +1671,27 @@ int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
(channel == MEM_DC_SYNC)) {
_ipu_dp_dc_disable(channel, false);
} else if (wait_for_stop) {
- if (idma_is_set(IDMAC_CHA_BUSY, in_dma) ||
+ while (idma_is_set(IDMAC_CHA_BUSY, in_dma) ||
idma_is_set(IDMAC_CHA_BUSY, out_dma) ||
(g_sec_chan_en[IPU_CHAN_ID(channel)] &&
idma_is_set(IDMAC_CHA_BUSY, sec_dma)) ||
(g_thrd_chan_en[IPU_CHAN_ID(channel)] &&
idma_is_set(IDMAC_CHA_BUSY, thrd_dma)) ||
(_ipu_channel_status(channel) == TASK_STAT_ACTIVE)) {
- uint32_t ret, irq = in_dma;
+ uint32_t ret, irq = out_dma;
DECLARE_COMPLETION_ONSTACK(disable_comp);
+ if (idma_is_set(IDMAC_CHA_BUSY, out_dma))
+ irq = out_dma;
+ if (g_sec_chan_en[IPU_CHAN_ID(channel)] &&
+ idma_is_set(IDMAC_CHA_BUSY, sec_dma))
+ irq = sec_dma;
+ if (g_thrd_chan_en[IPU_CHAN_ID(channel)] &&
+ idma_is_set(IDMAC_CHA_BUSY, thrd_dma))
+ irq = thrd_dma;
+ if (idma_is_set(IDMAC_CHA_BUSY, in_dma))
+ irq = in_dma;
+
ret = ipu_request_irq(irq, disable_chan_irq_handler, 0, NULL, &disable_comp);
if (ret < 0) {
dev_err(g_ipu_dev, "irq %d in use\n", irq);