video: tegra: host: gk20a add comp tag flushing

We need to flush the compression tag cache any time
we're flushing the "fb."  E.g.: right before power
gating.  Note: this technique probably does enough
to flush "fb" all by itself.  So we may remove the
later state of manual fb flush after further testing.

bug 1331831

Change-Id: Ibc7df2a7decf17a1485602e7b888c35f356912ca
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/259851
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

2 files changed, 56 insertions, 0 deletions

diff --git a/drivers/video/tegra/host/gk20a/hw_ltc_gk20a.h b/drivers/video/tegra/host/gk20a/hw_ltc_gk20a.h
index 3426b3a7959a..f6566a4c7c59 100644
--- a/drivers/video/tegra/host/gk20a/hw_ltc_gk20a.h
+++ b/drivers/video/tegra/host/gk20a/hw_ltc_gk20a.h
@@ -1638,6 +1638,26 @@ static inline u32 ltc_ltc0_ltss_intr_en_blkactivity_err_enabled_f(void)
 {
 	return 0x20000000;
 }
+static inline u32 ltc_ltss_g_elpg_r(void)
+{
+	return 0x0017e828;
+}
+static inline u32 ltc_ltss_g_elpg_flush_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 ltc_ltss_g_elpg_flush_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltss_g_elpg_flush_pending_v(void)
+{
+	return 1;
+}
+static inline u32 ltc_ltss_g_elpg_flush_pending_f(void)
+{
+	return 0x1;
+}
 static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
 {
 	return 0x0017e8c8;
diff --git a/drivers/video/tegra/host/gk20a/mm_gk20a.c b/drivers/video/tegra/host/gk20a/mm_gk20a.c
index db98b358c762..998f3e45ba46 100644
--- a/drivers/video/tegra/host/gk20a/mm_gk20a.c
+++ b/drivers/video/tegra/host/gk20a/mm_gk20a.c
@@ -2089,6 +2089,40 @@ clean_up:
 	return err;
 }
 
+/* Flushes the compression bit cache as well as "data".
+ * Note: the name here is a bit of a misnomer.  ELPG uses this
+ * internally... but ELPG doesn't have to be on to do it manually.
+ */
+static void gk20a_mm_g_elpg_flush(struct gk20a *g)
+{
+	u32 data;
+	s32 retry = 100;
+
+	nvhost_dbg_fn("");
+
+	/* Make sure all previous writes are committed to the L2. There's no
+	   guarantee that writes are to DRAM. This will be a sysmembar internal
+	   to the L2. */
+	gk20a_writel(g, ltc_ltss_g_elpg_r(),
+		     ltc_ltss_g_elpg_flush_pending_f());
+	do {
+		data = gk20a_readl(g, ltc_ltss_g_elpg_r());
+
+		if (ltc_ltss_g_elpg_flush_v(data) ==
+		    ltc_ltss_g_elpg_flush_pending_v()) {
+			nvhost_dbg_info("g_elpg_flush 0x%x", data);
+			retry--;
+			udelay(20);
+		} else
+			break;
+	} while (retry >= 0);
+
+	if (retry < 0)
+		nvhost_warn(dev_from_gk20a(g),
+			    "g_elpg_flush too many retries");
+
+}
+
 void gk20a_mm_fb_flush(struct gk20a *g)
 {
 	u32 data;
@@ -2096,6 +2130,8 @@ void gk20a_mm_fb_flush(struct gk20a *g)
 
 	nvhost_dbg_fn("");
 
+	gk20a_mm_g_elpg_flush(g);
+
 	/* Make sure all previous writes are committed to the L2. There's no
 	   guarantee that writes are to DRAM. This will be a sysmembar internal
 	   to the L2. */