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authorJon Mayo <jmayo@nvidia.com>2011-05-13 17:28:58 -0700
committerVarun Colbert <vcolbert@nvidia.com>2011-05-17 11:53:35 -0700
commit263e4e4ec418dd3e76925c49ac314425159d3d63 (patch)
treeb8be9857c848e96e3852f2ace8c4ab9efb4788c1 /drivers
parente1e2a385c8015a8d7ef1ee8d79421a7a3bff129c (diff)
ARM: tegra: dc: lower hdmi clock before set rate
choose a higher clock divider on hdmi before switching clock parents. This prevents hdmi from exceeding its DVFS clock limits. Change-Id: I09c23498bf6450cf19e91accb788715582c3befb Reviewed-on: http://git-master/r/31605 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/tegra/dc/hdmi.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/hdmi.c b/drivers/video/tegra/dc/hdmi.c
index bda63c28800f..f1ca9fafbef8 100644
--- a/drivers/video/tegra/dc/hdmi.c
+++ b/drivers/video/tegra/dc/hdmi.c
@@ -1326,6 +1326,7 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
int err;
unsigned long val;
unsigned i;
+ unsigned long oldrate;
/* enbale power, clocks, resets, etc. */
@@ -1335,6 +1336,11 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
*/
clk_enable(hdmi->disp1_clk);
clk_enable(hdmi->disp2_clk);
+
+ /* back off multiplier before attaching to parent at new rate. */
+ oldrate = clk_get_rate(hdmi->clk);
+ clk_set_rate(hdmi->clk, oldrate / 2);
+
tegra_dc_setup_clk(dc, hdmi->clk);
clk_set_rate(hdmi->clk, dc->mode.pclk);